公开(公告)号：US20160284730A1

公开(公告)日：2016-09-29

申请号：US15179318

申请日：2016-06-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Sateesh KOKA ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  Yao-Sheng LEE ,  George MATAMIS

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process. Additional embodiments include improving the quality of the interface between the semiconductor channel material and the underlying semiconductor layers in the memory opening which may be damaged by the bottom opening etch, including forming single crystal semiconductor channel material by epitaxial growth from the bottom surface of the memory opening and/or oxidizing surfaces exposed to the bottom opening etch and removing the oxidized surfaces prior to forming the channel material. Monolithic three-dimensional memory devices formed by the embodiment methods are also disclosed.

公开(公告)号：US20160293617A1

公开(公告)日：2016-10-06

申请号：US15177737

申请日：2016-06-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Thomas Jongwan KWON ,  Senaka KANAKAMEDALA ,  George MATAMIS

IPC: H01L27/115 ,  H01L21/285 ,  H01L29/788 ,  H01L21/311 ,  H01L21/3205 ,  H01L29/423 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L27/11556 ,  G11C16/0408 ,  G11C16/06 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02238 ,  H01L21/28273 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/31111 ,  H01L21/32055 ,  H01L27/11519 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/7883

Abstract: A method of making a monolithic three dimensional NAND string which contains a semiconductor channel and a plurality of control gate electrodes, includes selectively forming a plurality of discrete charge storage regions using atomic layer deposition. The plurality of discrete charge storage regions includes at least one of a metal or an electrically conductive metal oxide.

Abstract translation: 包括半导体通道和多个控制栅电极的单片三维NAND串的制造方法包括使用原子层沉积选择性地形成多个离散的电荷存储区域。 多个离散电荷存储区域包括金属或导电金属氧化物中的至少一种。