公开(公告)号：US20240063278A1

公开(公告)日：2024-02-22

申请号：US18500623

申请日：2023-11-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dai IWATA ,  Hokuto KODATE

IPC: H01L29/423 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/42364 ,  H01L27/0617 ,  H01L29/6656 ,  H01L29/0653

Abstract: A lateral extent of a gate electrode of a field effect transistor along a gate electrode direction that is perpendicular to a channel direction can be the same as a width of an underlying active region. A gate electrode of an additional field effect transistor may extend over a trench isolation structure that laterally surrounds the additional field effect transistor. Different types of electrodes may be formed by patterning a lower gate material layer and by patterning an upper gate material layer with different patterns such that patterned portions of the lower gate material layer are confined within areas of active regions, while patterned portions of the upper gate material layer extends outside of the areas of the active regions.

公开(公告)号：US20240063062A1

公开(公告)日：2024-02-22

申请号：US17821273

申请日：2022-08-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kouta ONOGI ,  Kazutaka YOSHIZAWA ,  Hokuto KODATE ,  Mitsuhiro TOGO ,  Takahito FUJITA

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/285 ,  H01L21/265 ,  H01L21/266 ,  H01L21/768 ,  H01L29/49 ,  H01L29/45 ,  H01L23/535 ,  H01L27/088

CPC classification number: H01L21/823475 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823443 ,  H01L29/4933 ,  H01L29/45 ,  H01L23/535 ,  H01L27/088

Abstract: A transistor includes a first active region and a second active region separated by a semiconductor channel, a gate stack structure including a gate dielectric and a gate electrode overlying the semiconductor channel, a gate contact via structure overlying and electrically connected to the gate electrode and having a top surface located in a first horizontal plane, a first active-region contact via structure overlying and electrically connected to the first active region, and having a top surface located within a second horizontal plane that underlies the first horizontal plane, a first connection line structure contacting a top surface of the first active-region contact via structure, and a first connection via structure contacting a top surface of the first connection line structure and having a top surface within the first horizontal plane.

公开(公告)号：US20240153994A1

公开(公告)日：2024-05-09

申请号：US18500802

申请日：2023-11-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hokuto KODATE ,  Kazutaka YOSHIZAWA

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A lateral extent of a gate electrode of a field effect transistor along a gate electrode direction that is perpendicular to a channel direction can be the same as a width of an underlying active region. A gate electrode of an additional field effect transistor may extend over a trench isolation structure that laterally surrounds the additional field effect transistor. Different types of electrodes may be formed by patterning a lower gate material layer and by patterning an upper gate material layer with different patterns such that patterned portions of the lower gate material layer are confined within areas of active regions, while patterned portions of the upper gate material layer extends outside of the areas of the active regions.

公开(公告)号：US20240147730A1

公开(公告)日：2024-05-02

申请号：US18500721

申请日：2023-11-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyokazu SHISHIDO ,  Kazutaka YOSHIZAWA ,  Dai IWATA ,  Hokuto KODATE

IPC: H10B43/40 ,  H10B41/40

CPC classification number: H10B43/40 ,  H10B41/40 ,  G11C16/08

Abstract: A lateral extent of a gate electrode of a field effect transistor along a gate electrode direction that is perpendicular to a channel direction can be the same as a width of an underlying active region. A gate electrode of an additional field effect transistor may extend over a trench isolation structure that laterally surrounds the additional field effect transistor. Different types of electrodes may be formed by patterning a lower gate material layer and by patterning an upper gate material layer with different patterns such that patterned portions of the lower gate material layer are confined within areas of active regions, while patterned portions of the upper gate material layer extends outside of the areas of the active regions.

公开(公告)号：US20220068915A1

公开(公告)日：2022-03-03

申请号：US17006265

申请日：2020-08-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hokuto KODATE ,  Hiroyuki OGAWA ,  Dai IWATA ,  Mitsuhiro TOGO

IPC: H01L27/06 ,  H01L21/8234

Abstract: At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip. Contacts are then formed to the capacitor or resistor structure. Sidewall spacers may be formed on the gate electrode prior to patterning the capacitor or resistor contacts to reduce damage to the underlying capacitor or resistor layers.

公开(公告)号：US20240072042A1

公开(公告)日：2024-02-29

申请号：US18500862

申请日：2023-11-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hokuto KODATE ,  Kazutaka YOSHIZAWA

IPC: H01L27/06 ,  H01L21/8238 ,  H01L29/423

CPC classification number: H01L27/0629 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823871 ,  H01L21/823878 ,  H01L28/60 ,  H01L29/42376

Abstract: A lateral extent of a gate electrode of a field effect transistor along a gate electrode direction that is perpendicular to a channel direction can be the same as a width of an underlying active region. A gate electrode of an additional field effect transistor may extend over a trench isolation structure that laterally surrounds the additional field effect transistor. Different types of electrodes may be formed by patterning a lower gate material layer and by patterning an upper gate material layer with different patterns such that patterned portions of the lower gate material layer are confined within areas of active regions, while patterned portions of the upper gate material layer extends outside of the areas of the active regions.

公开(公告)号：US20220069097A1

公开(公告)日：2022-03-03

申请号：US17006228

申请日：2020-08-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hokuto KODATE ,  Hiroyuki OGAWA ,  Dai IWATA ,  Mitsuhiro TOGO

IPC: H01L29/423 ,  H01L49/02 ,  H01L29/40 ,  H01L27/06

Abstract: At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip. Contacts are then formed to the capacitor or resistor structure. Sidewall spacers may be formed on the gate electrode prior to patterning the capacitor or resistor contacts to reduce damage to the underlying capacitor or resistor layers.