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公开(公告)号:US20240063278A1
公开(公告)日:2024-02-22
申请号:US18500623
申请日:2023-11-02
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Dai IWATA , Hokuto KODATE
IPC: H01L29/423 , H01L27/06 , H01L29/66 , H01L29/06
CPC classification number: H01L29/42364 , H01L27/0617 , H01L29/6656 , H01L29/0653
Abstract: A lateral extent of a gate electrode of a field effect transistor along a gate electrode direction that is perpendicular to a channel direction can be the same as a width of an underlying active region. A gate electrode of an additional field effect transistor may extend over a trench isolation structure that laterally surrounds the additional field effect transistor. Different types of electrodes may be formed by patterning a lower gate material layer and by patterning an upper gate material layer with different patterns such that patterned portions of the lower gate material layer are confined within areas of active regions, while patterned portions of the upper gate material layer extends outside of the areas of the active regions.
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公开(公告)号:US20220069097A1
公开(公告)日:2022-03-03
申请号:US17006228
申请日:2020-08-28
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Hokuto KODATE , Hiroyuki OGAWA , Dai IWATA , Mitsuhiro TOGO
IPC: H01L29/423 , H01L49/02 , H01L29/40 , H01L27/06
Abstract: At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip. Contacts are then formed to the capacitor or resistor structure. Sidewall spacers may be formed on the gate electrode prior to patterning the capacitor or resistor contacts to reduce damage to the underlying capacitor or resistor layers.
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公开(公告)号:US20240258317A1
公开(公告)日:2024-08-01
申请号:US18631240
申请日:2024-04-10
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Kiyokazu SHISHIDO , Hiroshi NAKATSUJI , Dai IWATA , Koichi MATSUNO
IPC: H01L27/092 , H01L21/762 , H01L27/02 , H01L27/06 , H01L29/423 , H01L29/66
CPC classification number: H01L27/0922 , H01L21/76224 , H01L27/0207 , H01L29/4236 , H01L29/42376 , H01L29/6656 , H01L27/0629
Abstract: A first field effect transistor includes a first active region and a first gate electrode that includes a first semiconductor gate electrode portion and a first metallic gate electrode portion. The first active region includes a first source region and a first drain region that are laterally spaced from each other by a first channel along a first channel direction. The first gate electrode laterally extends along a first gate electrode direction that is perpendicular to the first channel direction. A maximum lateral extent of the first metallic gate electrode portion along the first gate electrode direction is greater than a maximum lateral extent of the first semiconductor gate electrode portion along the first gate electrode direction.
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公开(公告)号:US20240147730A1
公开(公告)日:2024-05-02
申请号:US18500721
申请日:2023-11-02
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Kiyokazu SHISHIDO , Kazutaka YOSHIZAWA , Dai IWATA , Hokuto KODATE
Abstract: A lateral extent of a gate electrode of a field effect transistor along a gate electrode direction that is perpendicular to a channel direction can be the same as a width of an underlying active region. A gate electrode of an additional field effect transistor may extend over a trench isolation structure that laterally surrounds the additional field effect transistor. Different types of electrodes may be formed by patterning a lower gate material layer and by patterning an upper gate material layer with different patterns such that patterned portions of the lower gate material layer are confined within areas of active regions, while patterned portions of the upper gate material layer extends outside of the areas of the active regions.
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公开(公告)号:US20220068915A1
公开(公告)日:2022-03-03
申请号:US17006265
申请日:2020-08-28
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Hokuto KODATE , Hiroyuki OGAWA , Dai IWATA , Mitsuhiro TOGO
IPC: H01L27/06 , H01L21/8234
Abstract: At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip. Contacts are then formed to the capacitor or resistor structure. Sidewall spacers may be formed on the gate electrode prior to patterning the capacitor or resistor contacts to reduce damage to the underlying capacitor or resistor layers.
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公开(公告)号:US20220367449A1
公开(公告)日:2022-11-17
申请号:US17501163
申请日:2021-10-14
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Akihiro YUU , Dai IWATA , Hiroyuki OGAWA
IPC: H01L27/088 , H01L21/762 , G11C7/06 , H01L29/06
Abstract: A first field effect transistor contains a first active region including a source region, a drain region and a channel region located between the source region and the drain region, a first gate dielectric overlying the active region, and a first gate electrode overlying the first gate dielectric. A second field effect transistor contains a second active region including a source region, a drain region and a channel region located between the source region and the drain region, a second gate dielectric overlying the active region, a second gate electrode overlying the second gate dielectric. A trench isolation region surrounds the first and the second active regions. The first field effect transistor includes a fringe region in which the first gate electrode extends past the active region perpendicular to the source region to drain region direction and the second field effect transistor does not include the fringe region.
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公开(公告)号:US20220359690A1
公开(公告)日:2022-11-10
申请号:US17316015
申请日:2021-05-10
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Dai IWATA , Hiroshi NAKATSUJI , Hiroyuki OGAWA , Eiichi FUJIKURA
IPC: H01L29/423 , H01L29/66 , H01L27/07 , H01L21/8238 , H01L29/40
Abstract: A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.
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公开(公告)号:US20170236835A1
公开(公告)日:2017-08-17
申请号:US15434544
申请日:2017-02-16
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Tadashi NAKAMURA , Jin LIU , Kazuya TOKUNAGA , Marika GUNJI-YONEOKA , Matthias BAENNINGER , Hiroyuki KINOSHITA , Murshed CHOWDHURY , Jiyin XU , Dai IWATA , Hiroyuki OGAWA , Kazutaka YOSHIZAWA , Yasuaki YONEMOCHI
IPC: H01L27/11582 , H01L27/11519 , H01L29/788 , H01L29/06 , H01L29/10 , H01L23/528 , H01L27/11526 , H01L29/423 , H01L21/28 , H01L21/311 , H01L21/764 , H01L23/29 , H01L23/31 , H01L27/11521 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11556
CPC classification number: H01L27/11582 , H01L21/31111 , H01L21/764 , H01L23/291 , H01L23/3171 , H01L23/528 , H01L28/00 , H01L29/0649 , H01L29/1037 , H01L29/42372
Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.
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