公开(公告)号：US20190287866A1

公开(公告)日：2019-09-19

申请号：US15923516

申请日：2018-03-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Keisuke IZUMI ,  Naomi MATSUDA

IPC: H01L21/66 ,  B24B37/015 ,  B24B37/04 ,  H01L21/321

Abstract: A chemical mechanical polishing apparatus includes a liquid filled bladder that exerts force on the back of the substrate being polished. The bladder can be a multi-chamber bladder having chambers filled with different ratios of hot and cold water. Eddy current detection during the polishing can be used to control the polishing process parameters.

公开(公告)号：US20240178129A1

公开(公告)日：2024-05-30

申请号：US18349578

申请日：2023-07-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takayuki MAEKURA ,  Takaaki IWAI ,  Keisuke IZUMI

IPC: H01L23/522 ,  G11C16/04 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5226 ,  G11C16/0483 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and composite layers, where each of the composite layers contains an electrically conductive layer and a dielectric material plate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a respective vertical stack of memory elements and a vertical semiconductor channel and a plurality of integrated line-and-via structures. Each of the plurality of integrated line-and-via structures includes a conductive plate portion that contacts the electrically conductive layer of a respective one of the composite layers, and a conductive via portion that is adjoined to a top surface of the conductive plate portion and vertically extends through a respective overlying subset of the insulating layers and a subset of the dielectric material plates of the composite layers.

公开(公告)号：US20220254733A1

公开(公告)日：2022-08-11

申请号：US17174064

申请日：2021-02-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Genta MIZUNO ,  Kenzo IIZUKA ,  Satoshi SHIMIZU ,  Keisuke IZUMI ,  Tatsuya HINOUE ,  Yujin TERASAWA ,  Seiji SHIMABUKURO ,  Ryousuke ITOU ,  Yanli ZHANG ,  Johann ALSMEIER ,  Yusuke YOSHIDA

IPC: H01L23/00 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.

公开(公告)号：US20160322374A1

公开(公告)日：2016-11-03

申请号：US15211401

申请日：2016-07-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki SANO ,  Keisuke IZUMI

IPC: H01L27/115 ,  H01L21/768 ,  H01L21/3105 ,  H01L23/522

CPC classification number: H01L27/11556 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A recessed region can be formed on a semiconductor substrate, and peripheral semiconductor devices can be formed on a recessed horizontal surface of the semiconductor substrate. An alternating stack of insulating layers and sacrificial material layers are formed over the semiconductor substrate, and memory stack structures are formed therethrough. Contact openings extending to sacrificial material layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. Electrically conductive via structures extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liners.

Abstract translation: 可以在半导体衬底上形成凹陷区域，并且可以在半导体衬底的凹入的水平表面上形成外围半导体器件。 绝缘层和牺牲材料层的交替叠层形成在半导体衬底之上，并且通过其形成存储器堆叠结构。 延伸到位于不同深度处的牺牲材料层的接触开口可以通过在掩模层上迭代地修剪减薄层的顺序曝光掩模层中的更多数量的开口，以及将预先存在的接触开口 一级 延伸到位于不同级别的导电电极的导电通孔结构可以设置有自对准的绝缘衬垫。