公开(公告)号：US20220157966A1

公开(公告)日：2022-05-19

申请号：US17097841

申请日：2020-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati PRASAD ,  Joyeeta NAG ,  Seung-Yeul YANG ,  Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA

IPC: H01L29/51 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/78 ,  H01L21/28 ,  H01L21/3115 ,  H01L29/66

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

公开(公告)号：US20220131067A1

公开(公告)日：2022-04-28

申请号：US17081557

申请日：2020-10-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alan KALITSOV ,  Bhagwati PRASAD ,  Derek STEWART

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  H01L43/12 ,  H01L43/14

Abstract: A magnetoresistive memory device includes a magnetic tunnel junction including a free layer, at least two tunneling dielectric barrier layers, and at least one metallic quantum well layer. The quantum well layer leads to the resonant electron tunneling through the magnetic tunnel junction in such a way that it strongly enhances the tunneling probability for one of the magnetization states of the free layer, while this tunneling probability remains much smaller in the opposite magnetization state of the free layer. The device can be configured in a spin transfer torque device configuration, a voltage-controlled magnetic anisotropy, a voltage controlled exchange coupling device configuration, or a spin-orbit-torque device configuration.

公开(公告)号：US20220157852A1

公开(公告)日：2022-05-19

申请号：US17097757

申请日：2020-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati PRASAD ,  Joyeeta NAG ,  Seung-Yeul YANG ,  Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159 ,  H01L29/51 ,  H01L29/66

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

公开(公告)号：US20240064992A1

公开(公告)日：2024-02-22

申请号：US17821012

申请日：2022-08-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Kartik SONDHI ,  Raghuveer S. MAKALA ,  Tiffany SANTOS ,  Fei ZHOU ,  Joyeeta NAG ,  Bhagwati PRASAD

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/11597 ,  H01L27/11587 ,  H01L29/6684 ,  H01L29/78391

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

公开(公告)号：US20220131068A1

公开(公告)日：2022-04-28

申请号：US17081625

申请日：2020-10-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alan KALITSOV ,  Bhagwati PRASAD ,  Derek STEWART

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  H01L43/12 ,  H01L43/14 ,  G11C11/16 ,  G11C11/18

Abstract: A magnetoresistive memory device includes a magnetic tunnel junction including a free layer, at least two tunneling dielectric barrier layers, and at least one metallic quantum well layer. The quantum well layer leads to the resonant electron tunneling through the magnetic tunnel junction in such a way that it strongly enhances the tunneling probability for one of the magnetization states of the free layer, while this tunneling probability remains much smaller in the opposite magnetization state of the free layer. The device can be configured in a spin transfer torque device configuration, a voltage-controlled magnetic anisotropy, a voltage controlled exchange coupling device configuration, or a spin-orbit-torque device configuration.

公开(公告)号：US20240064991A1

公开(公告)日：2024-02-22

申请号：US17820997

申请日：2022-08-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kartik SONDHI ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Tiffany SANTOS ,  Fei ZHOU ,  Joyeeta NAG ,  Bhagwati PRASAD ,  Adarsh RAJASHEKHAR

IPC: H01L27/11597 ,  H01L27/1159

CPC classification number: H01L27/11597 ,  H01L27/1159

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

公开(公告)号：US20230307029A1

公开(公告)日：2023-09-28

申请号：US18048121

申请日：2022-10-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alan KALITSOV ,  Derek STEWART ,  Bhagwati PRASAD

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

CPC classification number: G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10 ,  G11C11/1673 ,  G11C11/1675

Abstract: A magnetoresistive memory cell includes a first terminal electrode, a second terminal electrode, and a magnetoresistive layer stack located between the first terminal electrode and the second terminal electrode and including, from one side to another, a reference layer, a dielectric tunnel barrier layer, a free layer, and a material layer having two different states of lattice deformation which have different average in-plane lattice constants and which are configured to apply different in-plane stress. The material layer may be a metal-insulator transition (MIT) material layer that exhibits a phase transition between an insulator state and a metal state.

公开(公告)号：US20220130442A1

公开(公告)日：2022-04-28

申请号：US17081678

申请日：2020-10-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alan KALITSOV ,  Bhagwati PRASAD ,  Derek STEWART

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  G11C11/18

Abstract: A magnetoresistive memory device includes a magnetic tunnel junction including a free layer, at least two tunneling dielectric barrier layers, and at least one metallic quantum well layer. The quantum well layer leads to the resonant electron tunneling through the magnetic tunnel junction in such a way that it strongly enhances the tunneling probability for one of the magnetization states of the free layer, while this tunneling probability remains much smaller in the opposite magnetization state of the free layer. The device can be configured in a spin transfer torque device configuration, a voltage-controlled magnetic anisotropy, a voltage controlled exchange coupling device configuration, or a spin-orbit-torque device configuration.

公开(公告)号：US20210074727A1

公开(公告)日：2021-03-11

申请号：US17081122

申请日：2020-10-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati PRASAD ,  Rahul SHARANGPANI

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

Abstract: An antiferroelectric memory device includes at least one antiferroelectric memory cell. Each of the at least one antiferroelectric memory cell includes a first electrode, a second electrode and a stack containing an antiferroelectric layer and a doped semiconductor layer or a ferroelectric layer located between the first and the second electrodes.

公开(公告)号：US20210066348A1

公开(公告)日：2021-03-04

申请号：US17081147

申请日：2020-10-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati PRASAD ,  Rahul SHARANGPANI

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02

Abstract: An antiferroelectric memory device includes at least one antiferroelectric memory cell. Each of the at least one antiferroelectric memory cell includes a first electrode, a second electrode and a stack containing an antiferroelectric layer and a doped semiconductor layer or a ferroelectric layer located between the first and the second electrodes.