公开(公告)号：US20240064992A1

公开(公告)日：2024-02-22

申请号：US17821012

申请日：2022-08-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Kartik SONDHI ,  Raghuveer S. MAKALA ,  Tiffany SANTOS ,  Fei ZHOU ,  Joyeeta NAG ,  Bhagwati PRASAD

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/11597 ,  H01L27/11587 ,  H01L29/6684 ,  H01L29/78391

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

公开(公告)号：US20220157852A1

公开(公告)日：2022-05-19

申请号：US17097757

申请日：2020-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati PRASAD ,  Joyeeta NAG ,  Seung-Yeul YANG ,  Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159 ,  H01L29/51 ,  H01L29/66

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

公开(公告)号：US20210407943A1

公开(公告)日：2021-12-30

申请号：US17406758

申请日：2021-08-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Joyeeta NAG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A memory device includes a first electrically conductive line laterally extending along a first horizontal direction, a memory pillar structure overlying and contacting the first electrically conductive line, the memory pillar structure includes a vertical stack of a ferroelectric material plate and a selector material plate, and a second electrically conductive line laterally extending along a second horizontal direction and overlying and contacting the memory pillar structure.

公开(公告)号：US20240064991A1

公开(公告)日：2024-02-22

申请号：US17820997

申请日：2022-08-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kartik SONDHI ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Tiffany SANTOS ,  Fei ZHOU ,  Joyeeta NAG ,  Bhagwati PRASAD ,  Adarsh RAJASHEKHAR

IPC: H01L27/11597 ,  H01L27/1159

CPC classification number: H01L27/11597 ,  H01L27/1159

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

公开(公告)号：US20220165937A1

公开(公告)日：2022-05-26

申请号：US17670842

申请日：2022-02-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jeffrey LILLE ,  Joyeeta NAG ,  Raghuveer S. MAKALA

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  G11C5/08

Abstract: A method of forming a magnetoresistive random access memory (MRAM) device includes providing a first die containing a selector material layer located over a first substrate, providing a second die containing a MRAM layer stack located over a second substrate, and bonding the first die to the second die.

公开(公告)号：US20220157966A1

公开(公告)日：2022-05-19

申请号：US17097841

申请日：2020-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati PRASAD ,  Joyeeta NAG ,  Seung-Yeul YANG ,  Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA

IPC: H01L29/51 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/78 ,  H01L21/28 ,  H01L21/3115 ,  H01L29/66

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.