公开(公告)号：US11011500B2

公开(公告)日：2021-05-18

申请号：US16816495

申请日：2020-03-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nagesh Vodrahalli ,  Shrikar Bhagath ,  Chih Yang Li ,  Srinivasan Sivaram ,  Rama Shukla

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. The semiconductor device may further include a CMOS logic circuit as part of the pair of semiconductor dies or in its own semiconductor die mounted to the pair of semiconductor dies.

公开(公告)号：US20240096850A1

公开(公告)日：2024-03-21

申请号：US17949069

申请日：2022-09-20

Applicant: SanDisk Technologies LLC

Inventor： Jayavel Pachamuthu ,  Srinivasan Sivaram ,  Masaaki Higashitani

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/48 ,  H01L25/18 ,  H01L25/50 ,  H01L24/16 ,  H01L2224/05026 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2924/04941

Abstract: An integrated controller, logic circuit and memory array (“CLM”) semiconductor device includes stacked controller, memory array logic circuit and memory array wafers, or individual dies diced therefrom, which together operate as a single, integrated semiconductor flash memory device. The memory array logic circuit dies and/or the memory array dies may be formed with full-thickness plated or filled vias connecting to bond pads on opposed surfaces of the dies. The bond pads of the respective stacked semiconductor dies may be aligned and affixed to each other to electrically and mechanically couple each of the semiconductor dies in the respective wafers together.

公开(公告)号：US20210104495A1

公开(公告)日：2021-04-08

申请号：US16816495

申请日：2020-03-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nagesh Vodrahalli ,  Shrikar Bhagath ,  Chih Yang Li ,  Srinivasan Sivaram ,  Rama Shukla

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. The semiconductor device may further include a CMOS logic circuit as part of the pair of semiconductor dies or in its own semiconductor die mounted to the pair of semiconductor dies.

公开(公告)号：US20240276740A1

公开(公告)日：2024-08-15

申请号：US18358638

申请日：2023-07-25

Applicant: SanDisk Technologies LLC

Inventor： Srinivasan Sivaram ,  Jayavel Pachamuthu

IPC: H10B80/00 ,  G11C11/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  G11C11/005 ,  H01L24/08 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/1443 ,  H01L2924/14511

Abstract: A memory system comprises a monolithic integration of a NAND die, a MRAM die and one or more control dies positioned in a same semiconductor package for high speed and high density non-volatile data storage. The MRAM die can be operated as a cache for the NAND die or to provide long term data storage for data not cached for the NAND die. In one embodiment, the NAND die comprises a plurality of NAND strings. The MRAM die comprises a MRAM structure. The one or more control dies comprise one or more control circuits for operating the NAND die and the MRAM die.