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公开(公告)号：US11657884B2
公开(公告)日：2023-05-23
申请号：US17403052
申请日：2021-08-16
CPC分类号： G11C16/3445 , G11C16/0433 , G11C16/08 , G11C16/14 , G11C16/26
摘要： A non-volatile memory system erasing groups of connected memory cells separately performs erase verify for memory cells connected to even word lines to generate even results and erase verify for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine if the erase verify process indicates that the erasing has successful completed. In addition, for each group of connected memory cells, a last even result for the group is compared to a last odd result for the group. Even if the erase verify indicated that the erasing has successfully completed, the system may determine that the erasing failed (i.e. due to a defect) if the number of groups of connected memory cells that have the last even result different than the last odd result is greater than a limit.
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公开(公告)号：US20230058836A1
公开(公告)日：2023-02-23
申请号：US17729331
申请日：2022-04-26
发明人： Jayavel Pachamuthu , Dana Lee , Jiahui Yuan
摘要： A non-volatile memory system performs an erase process followed by a program process to program blocks of memory cells. The erase process comprises erasing followed by erase verification. The system recovers data and records a strike for blocks that fail a read process. In response to a particular block having a strike, the system performs an odd/even compare process during the erase process for the particular blocks having the strike such that the odd/even compare process comprises determining whether a number of memory cells connected to even word lines that have a different erase verify result than memory cells connected to odd word lines is greater than a defect test threshold. The system retires blocks from further use for storing host data that fail the odd/even compare process even if the block passes erase verification.
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公开(公告)号：US11195820B2
公开(公告)日：2021-12-07
申请号：US16808128
申请日：2020-03-03
发明人： Daniel Linnen , Kirubakaran Periyannan , Jayavel Pachamuthu , Narendhiran Cr , Jay Dholakia , Everett Lyons, IV , Hoang Huynh , Dat Dinh
IPC分类号： H01L23/00 , H01L25/065 , H01L23/525
摘要： A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.
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公开(公告)号：US11139276B2
公开(公告)日：2021-10-05
申请号：US16808128
申请日：2020-03-03
发明人： Daniel Linnen , Kirubakaran Periyannan , Jayavel Pachamuthu , Narendhiran Cr , Jay Dholakia , Everett Lyons, IV , Hoang Huynh , Dat Dinh
IPC分类号： H01L23/00 , H01L25/065 , H01L23/525
摘要： A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.
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公开(公告)号：US11037631B2
公开(公告)日：2021-06-15
申请号：US16252300
申请日：2019-01-18
摘要： Strings of non-volatile memory cells include one or more joint regions adjacent to dummy non-volatile memory cells. During erase operations, different voltage levels are used for different dummy word lines coupled to respective dummy non-volatile memory cells. For example, a selection circuit may set a voltage level of a particular dummy word line to a voltage level greater than a different dummy word line. In another example, the selection circuit may determine a voltage level for a given dummy word line based on a distance between a non-volatile memory cell coupled to the given dummy word line and a selection device included in a string of non-volatile memory cells. Electron holes generated using the dummy word lines during erase operations may neutralize undesired trapped charges in a non-volatile memory string, thereby reducing disparity in erase times for different strings in the non-volatile memory circuit.
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公开(公告)号：US10991705B2
公开(公告)日：2021-04-27
申请号：US16556854
申请日：2019-08-30
IPC分类号： H01L27/11556 , H01L27/11519 , H01L27/11582 , H01L27/1157 , H01L27/11565 , H01L27/11524
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. An amorphous semiconductor material portion is formed at a bottom region of the memory opening. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion thereof, and a surface of the amorphous semiconductor material portion is physically exposed at a bottom of the opening in the memory film. An amorphous semiconductor channel material layer is formed on the exposed surface of the amorphous semiconductor material portion and over the memory film. A vertical semiconductor channel is formed by annealing the amorphous semiconductor material portion and the amorphous semiconductor channel material layer. The vertical semiconductor channel and contacts an entire top surface of an underlying semiconductor material portion.
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公开(公告)号：US09831118B1
公开(公告)日：2017-11-28
申请号：US15163236
申请日：2016-05-24
发明人： Liang Pang , Yingda Dong , Jayavel Pachamuthu , Ching-Huang Lu
IPC分类号： H01L21/768 , H01L27/115 , H01L23/532 , H01L21/28 , H01L23/528 , H01L23/522 , H01L27/1157 , H01L27/11582
CPC分类号： H01L21/7682 , H01L21/28282 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/5329 , H01L27/1157 , H01L27/11582 , H01L29/66833
摘要： Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, the memory device is provided with a reduced dielectric constant (k) in locations of a fringing electric field of the control gate. For example, portions of the dielectric layers can be replaced with a low-k material. One approach involves recessing the dielectric layer and providing a low-k material in the recess. Another approach involves doping a portion of the blocking oxide layer to reduce its dielectric constant. Another approach involves removing a portion of the blocking oxide layer. In another aspect, the memory device is provided with an increased dielectric constant adjacent to the control gates.
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公开(公告)号：US10128257B2
公开(公告)日：2018-11-13
申请号：US15906317
申请日：2018-02-27
发明人： Liang Pang , Jayavel Pachamuthu , Yingda Dong
IPC分类号： H01L27/115 , H01L27/11519 , H01L21/02 , H01L21/28 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/66 , H01L27/1158 , H01L27/11553
摘要： Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.
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公开(公告)号：US10121794B2
公开(公告)日：2018-11-06
申请号：US15279959
申请日：2016-09-29
发明人： Marika Gunji-Yoneoka , Atsushi Suyama , Jayavel Pachamuthu , Tsuyoshi Hada , Daewung Kang , Murshed Chowdhury , James Kai , Hiro Kinoshita , Tomoyuki Obu , Luckshitha Suriyasena Liyanage
IPC分类号： H01L27/115 , H01L27/11556 , H01L27/11524 , H01L27/11582 , H01L27/1157
摘要： An alternating stack of insulating layers and spacer material layers is formed over a semiconductor substrate. Memory openings are formed through the alternating stack. An optional silicon-containing epitaxial pedestal and a memory film are formed in each memory opening. After forming an opening through a bottom portion of the memory film within each memory opening, a germanium-containing semiconductor layer and a dielectric layer is formed in each memory opening. Employing the memory film and the dielectric layer as a crucible, a liquid phase epitaxy anneal is performed to convert the germanium-containing semiconductor layer into a germanium-containing epitaxial channel layer. A dielectric core and a drain region can be formed over the dielectric layer. The germanium-containing epitaxial channel layer is single crystalline, and can provide a higher charge carrier mobility than a polysilicon channel.
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公开(公告)号：US20180102375A1
公开(公告)日：2018-04-12
申请号：US15291871
申请日：2016-10-12
发明人： Liang Pang , Jayavel Pachamuthu , Yingda Dong
IPC分类号： H01L27/115 , H01L29/66 , H01L21/02 , H01L21/28
CPC分类号： H01L27/11519 , H01L21/02532 , H01L21/0262 , H01L21/28273 , H01L21/28282 , H01L27/11524 , H01L27/11553 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/1158 , H01L27/11582 , H01L29/66825 , H01L29/66833
摘要： Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.
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