公开(公告)号：US09728547B1

公开(公告)日：2017-08-08

申请号：US15159034

申请日：2016-05-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shingo Ohsaki ,  Hiroshi Kariya ,  Takuro Maede ,  Takeshi Kawamura

IPC: H01L29/792 ,  H01L27/11556 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L27/11582 ,  H01L21/3213 ,  H01L27/11563 ,  H01L27/11578 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519

CPC classification number: H01L27/1157 ,  H01L21/02178 ,  H01L21/02227 ,  H01L21/0228 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76831 ,  H01L27/11563 ,  H01L27/11578 ,  H01L27/11582 ,  H01L28/00

Abstract: Unwanted erosion of dielectric materials around a backside contact trench can be avoided or minimized employing an aluminum oxide liner. An aluminum oxide liner can be formed inside an insulating material layer in a backside contact trench to prevent collateral etching of the insulating material at an upper portion of the backside contact trench during an anisotropic etch that forms an insulating spacer. Alternatively, an aluminum oxide layer can be employed as a backside blocking dielectric layer. An upper portion of the aluminum oxide layer can be converted into an aluminum compound layer including aluminum and a non-metallic element other than oxygen at an upper portion of the trench, and can be employed as a protective layer during formation of a backside contact structure.

公开(公告)号：US09754999B1

公开(公告)日：2017-09-05

申请号：US15240998

申请日：2016-08-18

Applicant: SanDisk Technologies LLC

Inventor： Seje Takaki ,  Manabu Hayashi ,  Ryousuke Itou ,  Takuro Maede ,  Kengo Kajiwara ,  Tetsuya Yamada ,  Yusuke Oda

IPC: H01L27/11551 ,  H01L27/24 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L27/2454 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/249 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

Abstract: A method is provided that includes forming a transistor by forming a gate disposed in a first direction above a substrate, the gate including a first bridge portion and a second bridge portion, forming the first bridge portion extending in the first direction and disposed near a top of the gate, and forming the second bridge portion extending in the first direction and disposed near a bottom of the gate.

公开(公告)号：US09673257B1

公开(公告)日：2017-06-06

申请号：US15172483

申请日：2016-06-03

Applicant: SanDisk Technologies LLC

Inventor： Seje Takaki ,  Manabu Hayashi ,  Akira Nakada ,  Ryousuke Itou ,  Takuro Maede ,  Kengo Kajiwara ,  Tetsuya Yamada

IPC: H01L29/78 ,  H01L27/24 ,  H01L29/66 ,  H01L29/51 ,  H01L45/00 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/528 ,  H01L29/786 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C13/00 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L27/249 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/77 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/2454 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/78642 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

Abstract: A method is provided that includes forming a transistor by forming a first a rail gate disposed in a first direction above a substrate, forming a second rail gate disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a bridge section disposed between the first rail gate and the second rail gate.