公开(公告)号：US20200161209A1

公开(公告)日：2020-05-21

申请号：US16773436

申请日：2020-01-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Erik Nino TOLENTINO ,  Vemal Raja MANIKAM ,  Azhar ARIPIN

IPC: H01L23/373 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.

公开(公告)号：US20180033777A1

公开(公告)日：2018-02-01

申请号：US15612971

申请日：2017-06-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Francis J. CARNEY ,  Yenting WEN ,  Chee Hiong CHEW ,  Azhar ARIPIN

IPC: H01L25/07 ,  H01L21/027 ,  H01L21/56 ,  H01L23/367 ,  H01L25/00 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/074 ,  H01L21/0273 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3675 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: Forming a semiconductor package includes coupling electrically conductive elements with a substrate, coupling a first die with one or more of the electrically conductive elements, and at least partially encapsulating the first die and electrically conductive elements in a first mold layer. A first redistribution layer (RDL) is placed over the first mold layer and electrically coupled with the first die. A second die is coupled with the first RDL, and the second die and first RDL are at least partially encapsulated in a second mold layer. A second RDL is formed over the second mold layer and is electrically coupled with the second die. A third mold layer at least partially encapsulates the second RDL. A portion of the substrate is removed to expose (and a solder mask is applied to) surfaces of the electrically conductive elements and of the first mold layer to form a stacked embedded package.

公开(公告)号：US20180261525A1

公开(公告)日：2018-09-13

申请号：US15973873

申请日：2018-05-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Erik Nino TOLENTINO ,  Vemal Raja MANIKAM ,  Azhar ARIPIN

IPC: H01L23/373 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.

公开(公告)号：US20180211939A1

公开(公告)日：2018-07-26

申请号：US15926127

申请日：2018-03-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Francis J. CARNEY ,  Yenting WEN ,  Chee Hiong CHEW ,  Azhar ARIPIN

IPC: H01L25/07 ,  H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L21/027 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L25/074 ,  H01L21/0273 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Forming a semiconductor package includes coupling electrically conductive elements with a substrate, coupling a first die with one or more of the electrically conductive elements, and at least partially encapsulating the first die and electrically conductive elements in a first mold layer. A first redistribution layer (RDL) is placed over the first mold layer and electrically coupled with the first die. A second die is coupled with the first RDL, and the second die and first RDL are at least partially encapsulated in a second mold layer. A second RDL is formed over the second mold layer and is electrically coupled with the second die. A third mold layer at least partially encapsulates the second RDL. A portion of the substrate is removed to expose (and a solder mask is applied to) surfaces of the electrically conductive elements and of the first mold layer to form a stacked embedded package.