公开(公告)号：US20240145515A1

公开(公告)日：2024-05-02

申请号：US18558593

申请日：2022-04-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Swarnal BORTHAKUR ,  Mario M. PELELLA ,  Chandrasekharan KOTHANDARAMAN ,  Marc Allen SULFRIDGE ,  Yusheng LIN ,  Larry Duane KINSMAN

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14634 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L27/14636 ,  H01L24/13 ,  H01L24/32 ,  H01L24/80 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/13025 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/05442

Abstract: An integrated circuit package (34, 34′, 34″) may be implemented by stacked first, second, and third integrated circuit dies (40, 50, 60). The first and second dies (40, 50) may be bonded to each other using corresponding inter-die connection structures (74-1, 84-1) at respective interfacial surfaces facing the other die. The second die (50) may also include a metal layer (84-2) for connecting to the third die (60) at its interfacial surface with the first die (40). The metal layer (84-2) may be connected to a corresponding inter-die connection structure (64) on the side of the third die (60) facing the second die (50) through a conductive through-substrate via (84-2) and an additional metal layer (102) in a redistribution layer (96) between the second and third dies (50, 60). The third die (60) may have a different lateral outline than the second die (50).