公开(公告)号：US20160148997A1

公开(公告)日：2016-05-26

申请号：US15009380

申请日：2016-01-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Peter MOENS ,  Ana VILLAMOR ,  Piet VANMEERBEEK ,  Jaume ROIG-GUITART ,  Filip BOGMAN

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/76 ,  H01L21/265

CPC classification number: H01L29/0634 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/76 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein. In one embodiment, the doped region can be an ion implanted region formed within the localized superjunction structure. In another embodiment, the doped region can be an epitaxial layer having a graded dopant profile adjoining the localized superjunction structure. The charge imbalance can improve, among other things, unclamped inductive switching (UIS) performance.

Abstract translation: 在一个实施例中，提供了具有从主表面延伸的局部超连接结构的半导体衬底。 然后在局部超结结构附近形成掺杂区，以在其中产生电荷不平衡。 在一个实施例中，掺杂区域可以是形成在局部超结结构内的离子注入区域。 在另一个实施例中，掺杂区域可以是具有与局部超结构结构相邻的分级掺杂剂分布的外延层。 电荷不平衡可以改善，尤其是松开感应开关（UIS）性能。

公开(公告)号：US20160036431A1

公开(公告)日：2016-02-04

申请号：US14576604

申请日：2014-12-19

Applicant: Semiconductor Components Industries, LLC

Inventor： Jaume ROIG-GUITART ,  Filip BAUWENS ,  Chin Foong TONG

IPC: H03K17/10 ,  H02M3/158

CPC classification number: H03K17/102 ,  H02M1/32 ,  H02M3/158

Abstract: An electronic device can include a switch coupled to a switching node. In an embodiment, the switch has a breakdown voltage is less than 2.0 times the designed operating voltage. In another embodiment, the electronic device can further include another switch, wherein both switches are coupled to each other at a switching node. The switches can have different breakdown voltages. In a particular embodiment, either or both switches can include a field-effect transistor and a zener diode that are connected in parallel. The zener diode can be designed to breakdown at a relatively lower fraction of the designed operating voltage as compared to a conventional device. Embodiments can be used to reduce voltage overshoot and ringing at the switching node that may occur after changing the states of the first and second switches. Processes of forming the electronic device can be implemented without significant complexity.

Abstract translation: 电子设备可以包括耦合到交换节点的开关。 在一个实施例中，开关的击穿电压小于设计工作电压的2.0倍。 在另一个实施例中，电子设备还可以包括另一个交换机，其中两个交换机在交换节点处彼此耦合。 开关可以具有不同的击穿电压。 在特定实施例中，任一个或两个开关可以包括并联连接的场效应晶体管和齐纳二极管。 与常规器件相比，齐纳二极管可以设计成以设计的工作电压的相对较低的比例击穿。 实施例可以用于在改变第一和第二开关的状态之后可能发生的交换节点处的电压过冲和振铃。 可以在没有显着复杂性的情况下实现形成电子设备的过程。

公开(公告)号：US20220199764A1

公开(公告)日：2022-06-23

申请号：US17247796

申请日：2020-12-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jaume ROIG-GUITART ,  Fredrik ALLERSTAM ,  Thomas NEYER ,  Andrei KONSTANTINOV ,  Martin DOMEIJ ,  Jangkwon LIM

IPC: H01L29/06 ,  H01L29/16

Abstract: In a general aspect, a semiconductor device can include a substrate of a first conductivity type, an active region disposed in the substrate, and a termination region disposed in the substrate adjacent to the active region. The termination region can include a junction termination extension (JTE) of a second conductivity type, where the second conductivity type is opposite the first conductivity type. The JTE can have a first depletion stopper region disposed in an upper portion of the JTE, a second depletion stopper region disposed in a lower portion of the JTE, and a high carrier mobility region disposed between the first depletion stopper region and the second depletion stopper region.

公开(公告)号：US20220020872A1

公开(公告)日：2022-01-20

申请号：US17369479

申请日：2021-07-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Herbert DE VLEESCHOUWER ,  Jaume ROIG-GUITART ,  Peter MOENS ,  Mohammad Shawkat ZAMAN ,  Olivier TRESCASES

IPC: H01L29/778 ,  G01R31/26 ,  G01R19/00 ,  H01L29/20

Abstract: In an embodiment, a HEMT is formed to have a main transistor having a main active area and a sense transistor having a sense active area. An embodiment may include that the main active area is isolated from the sense active area.

公开(公告)号：US20210327886A1

公开(公告)日：2021-10-21

申请号：US16853613

申请日：2020-04-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jaume ROIG-GUITART ,  Aurore CONSTANT

IPC: H01L27/112 ,  H01L29/20 ,  H01L29/06 ,  H01L29/778 ,  H01L29/30 ,  H01L29/868 ,  H01L29/66 ,  H01L21/306 ,  H01L29/205

Abstract: An embodiment of a method of forming a programming element using a III/V semiconductor material may include forming one or more recesses in a first portion of a gate material and forming a first conductor on the one or more recesses.
In an embodiment, the method may include configuring a programming circuit to form a voltage across the one or more recesses that is greater than a breakdown voltage of the gate material underlying the one or more recesses.

公开(公告)号：US20230403003A1

公开(公告)日：2023-12-14

申请号：US18310153

申请日：2023-05-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jaume ROIG-GUITART ,  Dean E. PROBST ,  Ashok Challa

IPC: H03K17/16 ,  H03K17/0412 ,  H01L29/78 ,  H01L27/088 ,  H01L27/06

CPC classification number: H03K17/161 ,  H03K17/04123 ,  H01L29/7813 ,  H01L27/088 ,  H01L27/0629

Abstract: A circuit includes a metal-oxide semiconductor field-effect transistor (MOSFET) and a snubber circuit coupled between a drain and a source of the MOSFET. The snubber circuit includes a transistor disposed in parallel to the MOSFET. The transistor has a floating gate. The circuit further includes a capacitor in series with the transistor, and a resistor disposed parallel to the capacitor.

公开(公告)号：US20180212021A1

公开(公告)日：2018-07-26

申请号：US15416726

申请日：2017-01-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jaume ROIG-GUITART ,  Filip BAUWENS

IPC: H01L29/06

CPC classification number: H01L29/0634 ,  H01L29/0649 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/407 ,  H01L29/8083

Abstract: In at least some embodiments, a semiconductor device structure comprises a first surface comprising a source and a gate; a second surface comprising a drain; a substrate of a first type, wherein the substrate is in contact with the drain; a first column in contact with the substrate and the first surface of the device, the first column comprising a dielectric material; and a mirroring axis, wherein a centerline of the first column is disposed along the mirroring axis, forming a first device side and a second device side, wherein the first device side mirrors the second device side. The first device side comprises a column of a second type in contact with the first column, the substrate, and the first surface of the device; a second column of the first type in contact with the substrate and the second column; a third column of the first type in contact with the substrate and the second column; a first region of the first type disposed in contact with the third column; a second region of the first type disposed in contact with the source and with a third region of the first type; and a first trench comprising the second type and a first region of the second type, wherein the first region of the second type is in contact with a gate region.

公开(公告)号：US20170179825A1

公开(公告)日：2017-06-22

申请号：US15139921

申请日：2016-04-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jaume ROIG-GUITART ,  Filip BAUWENS

IPC: H02M3/158 ,  H02M1/08

CPC classification number: H02M1/08 ,  H02M3/158 ,  H03K17/102 ,  H03K17/6871 ,  H03K17/74 ,  H03K2017/6875 ,  H03K2217/0018

Abstract: A method and apparatus for switched mode power supply (SMPS) system includes circuitry configured to produce a voltage output based on an input voltage, the SMPS circuitry includes inductive, capacitive and switching elements configured to generate the voltage output. The switching elements include at least one set of cascode coupled devices, each set of cascode coupled devices including a high electron mobility transistor (HEMT) and one of a diode and a field effect transistor (FET) in a cascode coupling. A controller produces a signal to a gate terminal of the FET of the sets of cascode coupled devices to drive the HEMT switching rate to adjust the output voltage. The circuitry of the SMPS further includes circuitry to couple the substrate of at least one HEMT to a high voltage node of the SMPS system to reduce large voltage spikes or dv/dts.

公开(公告)号：US20250096679A1

公开(公告)日：2025-03-20

申请号：US18468400

申请日：2023-09-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jaume ROIG-GUITART ,  Dean E. PROBST

IPC: H02M3/158 ,  H03K17/687

Abstract: In a general aspect, a circuit includes a metal-oxide semiconductor field-effect transistor (MOSFET) having a gate, a source, and a drain. The MOSFET has a first breakdown voltage. The circuit also includes a clamping circuit coupled between the drain and the source. The clamping circuit including a diode having a second breakdown voltage that is less than the first breakdown voltage. A cathode of the diode is coupled with the drain of the MOSFET. The clamping circuit further includes an inductor having a first terminal coupled with an anode of the diode, and a second terminal coupled with the source of the MOSFET.

公开(公告)号：US20200251588A1

公开(公告)日：2020-08-06

申请号：US16451288

申请日：2019-06-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gary H. LOECHELT ,  Jaume ROIG-GUITART

IPC: H01L29/78 ,  H01L29/66

Abstract: Systems and methods of the disclosed embodiments include a semiconductor device that includes an N-doped pillar with a gate structure configured to control a signal between a drain and a source in response to a gate voltage signal. The semiconductor device may also include a P-doped pillar with a capacitive structure. The capacitive structure capacitively couples the P-doped pillar to the gate structure to reduce ringing in the gate voltage signal.