公开(公告)号：US20170294530A1

公开(公告)日：2017-10-12

申请号：US15092858

申请日：2016-04-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Peter MOENS ,  Jaume ROIG-GUITART ,  Marnix TACK ,  Johan Camiel Julia JANSSENS

IPC: H01L29/778 ,  H01L23/528 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L23/482 ,  H01L23/4824 ,  H01L27/0883 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/518 ,  H01L29/66462

Abstract: An electronic device can include a low-side HEMT including a segmented gate electrode; and a high-side HEMT coupled to the low-side HEMT, wherein the low-side and high voltage HEMTs are integrated within a same semiconductor die. In another aspect, an electronic device can include a source electrode; a low-side HEMT; a high-side HEMT coupled to the low-side HEMT; and a resistive element. In an embodiment, the resistive element can be coupled to the source electrode and a gate electrode of the high voltage HEMT, and in another embodiment, the resistive element can be coupled to the source electrode and a drain of the low-side HEMT. A process of forming an electronic device can include forming a channel layer over a substrate; and forming a gate electrode over the channel layer. The gate electrode can be a segmented gate electrode of a HEMT.

公开(公告)号：US20190371909A1

公开(公告)日：2019-12-05

申请号：US15997122

申请日：2018-06-04

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Abhishek BANERJEE ,  Piet VANMEERBEEK ,  Peter MOENS ,  Marnix TACK

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/778 ,  H01L21/28

Abstract: An electronic device can include a channel layer; an access region having an aluminum content substantially uniform or increasing with distance from the channel layer; and a gate dielectric layer overlying and contacting the channel layer. A process of forming an electronic device can include providing a substrate and a channel layer of a III-V semiconductor material over the substrate; forming a masking feature over the channel layer; and forming an access region over the channel layer. In an embodiment, the channel layer can include GaN, and the access region has an aluminum content that is substantially uniform or increases with distance from the channel layer. In another embodiment, the process can include removing at least a portion the masking feature and forming a gate dielectric layer over the channel layer. A dielectric film of the masking feature or the gate dielectric layer contacts the channel layer.

公开(公告)号：US20210210627A1

公开(公告)日：2021-07-08

申请号：US16734649

申请日：2020-01-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Peter MOENS ,  Piet VANMEERBEEK ,  Abhishek BANERJEE ,  Marnix TACK

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/51

Abstract: An Enhancement Mode (e-mode) Metal Insulator Semiconductor (MIS) High Electron Mobility Transistor (HEMT), or EMISHEMT, with GaN channel regrowth under a gate area, is described. The EMISHEMT with GaN channel regrowth under a gate area provides a normally-off device with a suitably high and stable threshold voltage, while providing a low gate leakage current. A channel layer provides a 2DEG and associated low on-resistance, while a channel-material layer extends through an etched recess and into the channel layer, and disrupts the 2DEG locally to enable the normally-off operation.

公开(公告)号：US20200006521A1

公开(公告)日：2020-01-02

申请号：US16025085

申请日：2018-07-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Abhishek BANERJEE ,  Piet VANMEERBEEK ,  Peter MOENS ,  Marnix TACK ,  Woochul JEON ,  Ali SALIH

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

Abstract: A process of forming an electronic device can include forming a channel layer overlying a substrate and forming a barrier layer overlying the channel layer. In an embodiment, the process can further include forming a p-type semiconductor layer over the barrier layer, patterning the p-type semiconductor layer to define at least part of a gate electrode of a transistor structure, and forming an access region layer over the barrier layer. In another embodiment, the process can further include forming an etch-stop layer over the barrier layer, forming a sacrificial layer over the etch-stop layer, patterning the etch-stop and sacrificial layers to define a gate region, forming an access region layer over the barrier layer after patterning the etch-stop and sacrificial layers, and forming a p-type semiconductor layer within the gate region.