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    ELECTRONIC DEVICE INCLUDING AN ACCESS REGION AND A PROCESS OF FORMING THE SAME
    1.
    发明申请
    ELECTRONIC DEVICE INCLUDING AN ACCESS REGION AND A PROCESS OF FORMING THE SAME 审中-公开

    公开(公告)号：US20190371909A1

    公开(公告)日：2019-12-05

    申请号：US15997122

    申请日：2018-06-04

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Abhishek BANERJEE ,  Piet VANMEERBEEK ,  Peter MOENS ,  Marnix TACK

    IPC: H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/778 ,  H01L21/28

    Abstract: An electronic device can include a channel layer; an access region having an aluminum content substantially uniform or increasing with distance from the channel layer; and a gate dielectric layer overlying and contacting the channel layer. A process of forming an electronic device can include providing a substrate and a channel layer of a III-V semiconductor material over the substrate; forming a masking feature over the channel layer; and forming an access region over the channel layer. In an embodiment, the channel layer can include GaN, and the access region has an aluminum content that is substantially uniform or increases with distance from the channel layer. In another embodiment, the process can include removing at least a portion the masking feature and forming a gate dielectric layer over the channel layer. A dielectric film of the masking feature or the gate dielectric layer contacts the channel layer.

    PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING AN ACCESS REGION
    3.
    发明申请
    PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING AN ACCESS REGION 审中-公开

    公开(公告)号：US20200006521A1

    公开(公告)日：2020-01-02

    申请号：US16025085

    申请日：2018-07-02

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Abhishek BANERJEE ,  Piet VANMEERBEEK ,  Peter MOENS ,  Marnix TACK ,  Woochul JEON ,  Ali SALIH

    IPC: H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

    Abstract: A process of forming an electronic device can include forming a channel layer overlying a substrate and forming a barrier layer overlying the channel layer. In an embodiment, the process can further include forming a p-type semiconductor layer over the barrier layer, patterning the p-type semiconductor layer to define at least part of a gate electrode of a transistor structure, and forming an access region layer over the barrier layer. In another embodiment, the process can further include forming an etch-stop layer over the barrier layer, forming a sacrificial layer over the etch-stop layer, patterning the etch-stop and sacrificial layers to define a gate region, forming an access region layer over the barrier layer after patterning the etch-stop and sacrificial layers, and forming a p-type semiconductor layer within the gate region.

    Electronic Device Including a HEMT Including a Buried Region
    5.
    发明申请
    Electronic Device Including a HEMT Including a Buried Region 审中-公开

    公开(公告)号：US20200219871A1

    公开(公告)日：2020-07-09

    申请号：US16241172

    申请日：2019-01-07

    Applicant: Semiconductor Components Industries, LLC

    Inventor： Peter MOENS ,  Arno Stockman ,  Piet VANMEERBEEK ,  Abhishek BANERJEE ,  Frederick Johan G. DECLERCQ

    IPC: H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778

    Abstract: An electronic device can include a high electron mobility transistor that includes a buried region, a channel layer overlying the buried region, a gate electrode, and a drain electrode overlying the buried region. The buried region can extend toward and does not underlie the gate electrode. In a particular aspect, the electronic device can further include a p-type semiconductor member overlying the channel layer. The gate electrode can overlie the channel layer, a p-type semiconductor member overlying the channel layer. The drain electrode can overlie and contact the buried region and the p-type semiconductor member. The p-type semiconductor member can be disposed between the gate and drain electrodes. In another embodiment, a source-side buried region may be used in addition to or in place of the buried region that is coupled to the drain electrode.

    PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A TRANSISTOR STRUCTURE
    6.
    发明申请
    PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A TRANSISTOR STRUCTURE 审中-公开

    公开(公告)号：US20190035910A1

    公开(公告)日：2019-01-31

    申请号：US15662622

    申请日：2017-07-28

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Peter MOENS ,  Abhishek BANERJEE

    IPC: H01L29/66 ,  H01L29/20 ,  H01L29/32 ,  H01L29/778 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324

    Abstract: An electronic device including a transistor structure, and a process of forming the electronic device can include providing a workpiece including a substrate, a first layer, and a channel layer including a compound semiconductor material; and implanting a species into the workpiece such that the projected range extends at least into the channel and first layers, and the implant is performed into an area corresponding to at least a source region of the transistor structure. In an embodiment, the area corresponds to substantially all area occupied by the transistor structure. In another embodiment, the implant can form crystal defects within layers between the substrate and source, gate, and drain electrodes. The crystal defects may allow resistive coupling between the substrate and the channel structure within the transistor structure. The resistive coupling allows for better dynamic on-state resistance and potentially other electrical properties.

    ELECTRONIC DEVICE INCLUDING A TRANSISTOR AND A CURRENT LIMITING CONTROL STRUCTURE
    8.
    发明申请
    ELECTRONIC DEVICE INCLUDING A TRANSISTOR AND A CURRENT LIMITING CONTROL STRUCTURE 审中-公开

    公开(公告)号：US20200083361A1

    公开(公告)日：2020-03-12

    申请号：US16123115

    申请日：2018-09-06

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Peter MOENS ,  Abhishek BANERJEE ,  Piet VANMEERBEEK

    IPC: H01L29/778 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L27/07 ,  H01L29/47 ,  H01L29/66

    Abstract: An electronic device can include a drain electrode of a high electron mobility transistor overlying a channel layer; a source electrode overlying the channel layer, wherein a lowermost portion of the source electrode overlies at least a portion of the channel layer; and a gate electrode of the high electron mobility transistor overlying the channel layer; and a current limiting control structure that controls current passing between the drain and source electrodes. The current limiting control structure can be disposed between the source and gate electrodes, the current limiting control structure can be coupled to the source electrode and the first high electron mobility transistor, and the current limiting control structure has a threshold voltage. The current limiting control structure can be a Schottky-gated HEMT or a MISHEMT.

    OHMIC CONTACT STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD
    9.
    发明申请
    OHMIC CONTACT STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD 有权
    用于半导体器件和方法的OHMIC接触结构

    公开(公告)号：US20140264454A1

    公开(公告)日：2014-09-18

    申请号：US14191030

    申请日：2014-02-26

    Applicant: Semiconductor Components Industries, LLC

    Inventor： Abhishek BANERJEE ,  Peter MOENS

    IPC: H01L29/778 ,  H01L29/66

    CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462

    Abstract: In one embodiment, a high electron mobility device structure includes heterostructure with a Group III-nitride channel layer and a Group III-nitride barrier layer that forms a two-dimensional electron gas layer at an interface between the two layers. At least one current carrying electrode includes a recess-structured conductive contact adjoining and making Ohmic contact with the two-dimensional electron gas layer. The recess-structured conductive contact has at least one side surface defined to have a rounded wavy shape.

    Abstract translation: 在一个实施例中，高电子迁移率器件结构包括具有III族氮化物沟道层的异质结构和在两层之间的界面处形成二维电子气体层的III族氮化物势垒层。 至少一个载流电极包括邻接并与二维电子气体层进行欧姆接触的凹陷结构的导电接触。 凹陷结构的导电接触件具有限定为具有圆形波状形状的至少一个侧表面。

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