公开(公告)号：US20180197851A1

公开(公告)日：2018-07-12

申请号：US15911999

申请日：2018-03-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul JEON ,  Ali SALIH

IPC: H01L27/06 ,  H01L29/778 ,  H01L29/20 ,  H01L29/417 ,  H01L29/40 ,  H01L49/02 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L29/7787 ,  H01L27/0883 ,  H01L28/40 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786

Abstract: In an aspect, a cascode circuit can include a high-side transistor and a low-side transistor. The source of the high-side transistor can be coupled to the drain of the low-side transistor; and the gate of the high-side transistor can be coupled to each of the source and the gate of the low-side transistor. In another aspect, an electronic device can include a high-side transistor, a low-side transistor, and a field electrode. The low-side transistor can include a drain region coupled to the source electrode of the high-side transistor. The field electrode can overlie and be capacitively coupled to a channel layer of the high-side transistor, wherein the field electrode is configured to be at a voltage between the voltages of the high-side and low-side power supply terminals.

公开(公告)号：US20160172234A1

公开(公告)日：2016-06-16

申请号：US15047874

申请日：2016-02-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  Zia HOSSAIN ,  Ali SALIH

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L21/76205 ,  H01L21/76816 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: In an embodiment, a method of forming a semiconductor may include forming a plurality of active trenches and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches. The method may also include forming at least one active trench of the plurality of active trenches having corners linking trench ends to sides of active trenches wherein each active trench of the plurality of active trenches has a first profile along the first length and a second profile at or near the trench ends; and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches and having a second profile wherein one of the first profile or the second profile includes a non-linear shape.

公开(公告)号：US20160064325A1

公开(公告)日：2016-03-03

申请号：US14939873

申请日：2015-11-12

Applicant: Semiconductor Components Industries, LLC

Inventor： Ali SALIH ,  Chun-Li LIU ,  Gordon M. GRIVNA

IPC: H01L23/522 ,  H01L23/532 ,  H01L29/778

CPC classification number: H01L23/5226 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/4824 ,  H01L23/49827 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/84 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L2221/68327 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/04034 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/37012 ,  H01L2224/37013 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/3716 ,  H01L2224/37187 ,  H01L2224/3719 ,  H01L2224/37639 ,  H01L2224/37644 ,  H01L2224/37647 ,  H01L2224/37655 ,  H01L2224/37664 ,  H01L2224/40499 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/07811 ,  H01L2224/45099

Abstract: In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.

Abstract translation: 在一个实施例中，形成HEMT器件的方法可以包括将导体或多个导体电镀到覆盖在HEMT器件的多个载流电极上的绝缘体上。 该方法还可以包括将连接器附接到导体上或者将多个连接器附接到多个导体上。

公开(公告)号：US20210104415A1

公开(公告)日：2021-04-08

申请号：US17123269

申请日：2020-12-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Ali SALIH

IPC: H01L21/324 ,  H01L21/322 ,  H01L21/02 ,  H01L29/20 ,  H01L29/786 ,  H01L29/66

Abstract: Systems and methods of the disclosed embodiments include reducing defects in a semiconductor layer. The defects may be reduced by forming the semiconductor layer on a substrate, removing at least a portion the substrate from an underside of the semiconductor layer, and annealing the semiconductor layer to reduce the defects in the layer. The annealing includes focusing energy at the layer.

公开(公告)号：US20210013336A1

公开(公告)日：2021-01-14

申请号：US16947593

申请日：2020-08-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul JEON ,  Ali SALIH ,  Llewellyn Vaughan-Edmunds

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/08 ,  H01L29/872 ,  H01L29/66

Abstract: High-electron-mobility transistor (HEMT) devices are described in this patent application. In some implementations, the HEMT devices can include a back barrier hole injection structure. In some implementations, the HEMT devices include a conductive striped portion electrically coupled to a drain contact.

公开(公告)号：US20180096993A1

公开(公告)日：2018-04-05

申请号：US15286042

申请日：2016-10-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul JEON ,  Ali SALIH

IPC: H01L27/088 ,  H01L29/778

CPC classification number: H01L27/0883 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/7786

Abstract: An electronic device can include a first transistor including a first gate electrode; and a second transistor including a second gate electrode. The first and second transistors can be electrically connected in a parallel arrangement, wherein the transistors have one or more different characteristics. For example, gate length, barrier layer thickness, gate-to-drain distance, leakage current, on-state electron density, or the like may be different between the transistors. The difference in characteristics can help to reduce degradation and improve the lifetime of the first transistor.

公开(公告)号：US20180033669A1

公开(公告)日：2018-02-01

申请号：US15225607

申请日：2016-08-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Ali SALIH ,  Gordon M. GRIVNA

IPC: H01L21/683 ,  H01L21/56 ,  H01L23/31 ,  H01L21/304 ,  H01L21/306 ,  H01L29/778 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L21/304 ,  H01L21/306 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/8258 ,  H01L23/3178 ,  H01L23/3192 ,  H01L24/95 ,  H01L27/0694 ,  H01L27/085 ,  H01L29/16 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/7786 ,  H01L29/7816 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: An electronic device can include a semiconductor material and a semiconductor layer overlying the semiconductor material, wherein the semiconductor layer has a greater bandgap energy as compared to the semiconductor material. The electronic device can include a component having a high electrical field region and a low electrical field region. Within the high electrical field region, the semiconductor material is not present. In another embodiment, the component may not be present. In another aspect, a process can include providing a substrate and a semiconductor layer overlying the substrate; removing a first portion of the substrate to define a first trench; forming a first insulating layer within the first trench; removing a second portion of the substrate adjacent to first insulating layer to define second trench; and forming a second insulating layer within the second trench.

公开(公告)号：US20200006521A1

公开(公告)日：2020-01-02

申请号：US16025085

申请日：2018-07-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Abhishek BANERJEE ,  Piet VANMEERBEEK ,  Peter MOENS ,  Marnix TACK ,  Woochul JEON ,  Ali SALIH

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

Abstract: A process of forming an electronic device can include forming a channel layer overlying a substrate and forming a barrier layer overlying the channel layer. In an embodiment, the process can further include forming a p-type semiconductor layer over the barrier layer, patterning the p-type semiconductor layer to define at least part of a gate electrode of a transistor structure, and forming an access region layer over the barrier layer. In another embodiment, the process can further include forming an etch-stop layer over the barrier layer, forming a sacrificial layer over the etch-stop layer, patterning the etch-stop and sacrificial layers to define a gate region, forming an access region layer over the barrier layer after patterning the etch-stop and sacrificial layers, and forming a p-type semiconductor layer within the gate region.

公开(公告)号：US20180068997A1

公开(公告)日：2018-03-08

申请号：US15260185

申请日：2016-09-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul JEON ,  Ali SALIH

IPC: H01L27/06 ,  H01L23/528 ,  H01L49/02 ,  H01L29/40 ,  H01L27/088 ,  H01L29/417 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/7787 ,  H01L27/0883 ,  H01L28/40 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786

Abstract: In an aspect, a cascode circuit can include a high-side transistor and a low-side transistor. The source of the high-side transistor can be coupled to the drain of the low-side transistor; and the gate of the high-side transistor can be coupled to each of the source and the gate of the low-side transistor. In another aspect, an electronic device can include a high-side transistor, a low-side transistor, and a field electrode. The low-side transistor can include a drain region coupled to the source electrode of the high-side transistor. The field electrode can overlie and be capacitively coupled to a channel layer of the high-side transistor, wherein the field electrode is configured to be at a voltage between the voltages of the high-side and low-side power supply terminals.

公开(公告)号：US20170358647A1

公开(公告)日：2017-12-14

申请号：US15581170

申请日：2017-04-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Peter MOENS ,  Jia GUO ,  Ali SALIH ,  Chun-Li LIU

IPC: H01L29/10 ,  H01L29/205 ,  H01L29/417 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7783 ,  H01L21/0254 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66431 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7782 ,  H01L29/7787 ,  H01L2924/13064

Abstract: An electronic device can include a HEMT including at least two channel layers. In an embodiment, a lower semiconductor layer overlies a lower channel layer, wherein the lower semiconductor layer has an aluminum content that is at least 10% of a total metal content of the lower semiconductor layer. An upper semiconductor layer overlies the upper channel layer, wherein the upper semiconductor layer has an aluminum content that is greater as compared to the lower semiconductor layer. In another embodiment, an electronic device can include stepped source and drain electrodes, so that lower contact resistance can be achieved. In a further embodiment, an absolute value of a difference between pinch-off or threshold voltages between different channel layers is greater than 1 V and allows current to be turned on or turned off for a channel layer without affecting another channel layer.