公开(公告)号：US20210013336A1

公开(公告)日：2021-01-14

申请号：US16947593

申请日：2020-08-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul JEON ,  Ali SALIH ,  Llewellyn Vaughan-Edmunds

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/08 ,  H01L29/872 ,  H01L29/66

Abstract: High-electron-mobility transistor (HEMT) devices are described in this patent application. In some implementations, the HEMT devices can include a back barrier hole injection structure. In some implementations, the HEMT devices include a conductive striped portion electrically coupled to a drain contact.

公开(公告)号：US20180096993A1

公开(公告)日：2018-04-05

申请号：US15286042

申请日：2016-10-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul JEON ,  Ali SALIH

IPC: H01L27/088 ,  H01L29/778

CPC classification number: H01L27/0883 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/7786

Abstract: An electronic device can include a first transistor including a first gate electrode; and a second transistor including a second gate electrode. The first and second transistors can be electrically connected in a parallel arrangement, wherein the transistors have one or more different characteristics. For example, gate length, barrier layer thickness, gate-to-drain distance, leakage current, on-state electron density, or the like may be different between the transistors. The difference in characteristics can help to reduce degradation and improve the lifetime of the first transistor.

公开(公告)号：US20200013886A1

公开(公告)日：2020-01-09

申请号：US16026897

申请日：2018-07-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul JEON ,  Prasad VENKATRAMAN

IPC: H01L29/778 ,  H01L27/088 ,  H01L27/06

Abstract: An electronic device can include a channel layer and a barrier layer overlying the channel layer. In an embodiment, the electronic device can include a component disposed along a current path between a gate terminal and a gate electrode of a first transistor. In another embodiment, the electronic device can include a second transistor wherein source and gate electrodes of the second transistor are coupled to the gate electrode of the first transistor, and a drain electrode of the second transistor is coupled to the gate terminal. A circuit can include a transistor and a diode. The transistor can include a drain, a gate, and a source, wherein the drain is coupled to a drain terminal, and the source is coupled to a source terminal. The diode can have an anode is coupled to the gate terminal, and a cathode is coupled to a gate of the transistor.

公开(公告)号：US20180350964A1

公开(公告)日：2018-12-06

申请号：US16054254

申请日：2018-08-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul JEON ,  Chun-Li LIU

IPC: H01L29/778 ,  H01L23/535 ,  H01L29/20 ,  H01L29/417

CPC classification number: H01L29/7787 ,  H01L23/4824 ,  H01L23/535 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/7786

Abstract: Implementations of semiconductor devices may include: a first layer with a plurality of cells, each cell having a drain finger, a source finger and a gate ring; a second layer having a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad; wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer; and wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact.

公开(公告)号：US20180240791A1

公开(公告)日：2018-08-23

申请号：US15438675

申请日：2017-02-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul JEON

IPC: H01L27/02 ,  H01L29/88 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/2003 ,  H01L21/8252 ,  H01L27/0255 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/0727 ,  H01L29/205 ,  H01L29/8613

Abstract: In one embodiment, a method of forming a HEM diode may comprise forming the HEM diode with high forward voltage that is greater than one of a gate-to-source threshold voltage of a HEMT or a forward voltage of a P-N diode.

公开(公告)号：US20160118379A1

公开(公告)日：2016-04-28

申请号：US14853729

申请日：2015-09-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji PADMANABHAN ,  Prasad VENKATRAMAN ,  Zia HOSSAIN ,  Chun-Li LIU ,  Woochul JEON ,  Jason MCDONALD

IPC: H01L27/06 ,  H01L23/535 ,  H01L29/872 ,  H01L29/778 ,  H01L29/205

CPC classification number: H01L27/0629 ,  H01L21/743 ,  H01L21/8258 ,  H01L23/3677 ,  H01L23/481 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0688 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/7783 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes.

Abstract translation: 在一个实施例中，共源共栅整流器结构包括III-V族半导体结构，其包括设置在半导体衬底上的异质结构。 第一载流电极和第二载流电极邻近异质结构的主表面设置，并且控制电极设置在第一和第二载流电极之间。 整流器件与III-V族半导体结构集成，并与第一载流电极和第三电极电连接。 控制电极进一步电连接到半导体衬底，第二电流通路大致垂直于第一和第二载流电极之间的初级电流通路。

公开(公告)号：US20200006521A1

公开(公告)日：2020-01-02

申请号：US16025085

申请日：2018-07-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Abhishek BANERJEE ,  Piet VANMEERBEEK ,  Peter MOENS ,  Marnix TACK ,  Woochul JEON ,  Ali SALIH

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

Abstract: A process of forming an electronic device can include forming a channel layer overlying a substrate and forming a barrier layer overlying the channel layer. In an embodiment, the process can further include forming a p-type semiconductor layer over the barrier layer, patterning the p-type semiconductor layer to define at least part of a gate electrode of a transistor structure, and forming an access region layer over the barrier layer. In another embodiment, the process can further include forming an etch-stop layer over the barrier layer, forming a sacrificial layer over the etch-stop layer, patterning the etch-stop and sacrificial layers to define a gate region, forming an access region layer over the barrier layer after patterning the etch-stop and sacrificial layers, and forming a p-type semiconductor layer within the gate region.

公开(公告)号：US20200006202A1

公开(公告)日：2020-01-02

申请号：US16569218

申请日：2019-09-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul JEON ,  Chun-Li LIU

IPC: H01L23/482 ,  H01L29/778 ,  H01L29/20 ,  H01L29/417 ,  H01L23/535

Abstract: Implementations of semiconductor devices may include: a first layer with a plurality of cells, each cell having a drain finger, a source finger and a gate ring; a second layer having a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad; wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer; and wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact.

公开(公告)号：US20190123043A1

公开(公告)日：2019-04-25

申请号：US16225930

申请日：2018-12-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji PADMANABHAN ,  Prasad VENKATRAMAN ,  Zia HOSSAIN ,  Chun-Li LIU ,  Woochul JEON ,  Jason MCDONALD

IPC: H01L27/06 ,  H01L29/10 ,  H01L27/02 ,  H01L23/367 ,  H01L29/417 ,  H01L29/778 ,  H01L21/74 ,  H01L21/8258

Abstract: A method for forming a cascode rectifier structure includes providing a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are provided adjacent a major surface of the heterostructure and a control electrode is provided between the first and second current carrying electrode. A rectifier device is provided integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is provided further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes. The cascode rectifier structure is provided as a two terminal device.

公开(公告)号：US20180068997A1

公开(公告)日：2018-03-08

申请号：US15260185

申请日：2016-09-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul JEON ,  Ali SALIH

IPC: H01L27/06 ,  H01L23/528 ,  H01L49/02 ,  H01L29/40 ,  H01L27/088 ,  H01L29/417 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/7787 ,  H01L27/0883 ,  H01L28/40 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786

Abstract: In an aspect, a cascode circuit can include a high-side transistor and a low-side transistor. The source of the high-side transistor can be coupled to the drain of the low-side transistor; and the gate of the high-side transistor can be coupled to each of the source and the gate of the low-side transistor. In another aspect, an electronic device can include a high-side transistor, a low-side transistor, and a field electrode. The low-side transistor can include a drain region coupled to the source electrode of the high-side transistor. The field electrode can overlie and be capacitively coupled to a channel layer of the high-side transistor, wherein the field electrode is configured to be at a voltage between the voltages of the high-side and low-side power supply terminals.