公开(公告)号：US12183747B2

公开(公告)日：2024-12-31

申请号：US18436245

申请日：2024-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Okazaki ,  Tomoaki Moriwaka ,  Shinya Sasagawa ,  Takashi Ohtsuki

IPC: H01L29/66 ,  H01L21/768 ,  H01L27/12 ,  H01L29/786 ,  H01L23/532

Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

公开(公告)号：US11310457B2

公开(公告)日：2022-04-19

申请号：US16663403

申请日：2019-10-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Satoshi Murakami ,  Motomu Kurata ,  Hiroyuki Hata ,  Mitsuhiro Ichijo ,  Takashi Ohtsuki ,  Aya Anzai ,  Masayuki Sakakura

IPC: H01L27/14 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  H04N5/655 ,  H01L27/12 ,  H01L27/32 ,  H01L51/52 ,  H01L33/60 ,  G06F3/02 ,  H04N5/64 ,  H01L51/00 ,  H01L51/56

Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.

公开(公告)号：US09722056B2

公开(公告)日：2017-08-01

申请号：US15276993

申请日：2016-09-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Akihisa Shimomura ,  Yasumasa Yamane ,  Yuhei Sato ,  Tetsuhiro Tanaka ,  Masashi Tsubuku ,  Toshihiko Takeuchi ,  Ryo Tokumaru ,  Mitsuhiro Ichijo ,  Satoshi Toriumi ,  Takashi Ohtsuki ,  Toshiya Endo

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. Oxygen is introduced into a surface of an insulating film, and then, an oxide semiconductor, a layer which is capable of blocking oxygen, a gate insulating film, and other films which composes a transistor are formed. For at least one of the first gate insulating film and the insulating film, three signals in Electron Spin Resonance Measurement are each observed in a certain range of g-factor. Reducing the sum of the spin densities of the signals will improve reliability of the semiconductor device.

公开(公告)号：US20150179810A1

公开(公告)日：2015-06-25

申请号：US14575052

申请日：2014-12-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Akihisa Shimomura ,  Yasumasa Yamane ,  Yuhei Sato ,  Tetsuhiro Tanaka ,  Masashi Tsubuku ,  Toshihiko Takeuchi ,  Ryo Tokumaru ,  Mitsuhiro Ichijo ,  Satoshi Toriumi ,  Takashi Ohtsuki ,  Toshiya Endo

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. The semiconductor device includes an oxide semiconductor film over an insulating surface, an antioxidant film over the insulating surface and the oxide semiconductor film, a pair of electrodes in contact with the antioxidant film, a gate insulating film over the pair of electrodes, and a gate electrode which is over the gate insulating film and overlaps with the oxide semiconductor film. In the antioxidant film, a width of a region overlapping with the pair of electrodes is longer than a width of a region not overlapping with the pair of electrodes.

Abstract translation: 抑制了电特性的变化，并且提高了使用包括氧化物半导体的晶体管的半导体器件的可靠性。 半导体器件包括绝缘表面上的氧化物半导体膜，绝缘表面上的抗氧化膜和氧化物半导体膜，与抗氧化膜接触的一对电极，一对电极上的栅极绝缘膜，以及栅极 电极，其在栅极绝缘膜上方并与氧化物半导体膜重叠。 在抗氧化剂膜中，与该对电极重叠的区域的宽度比不与该对电极重叠的区域的宽度长。

公开(公告)号：US10304864B2

公开(公告)日：2019-05-28

申请号：US15708714

申请日：2017-09-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Okazaki ,  Tomoaki Moriwaka ,  Shinya Sasagawa ,  Takashi Ohtsuki

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L21/768 ,  H01L23/532

Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

公开(公告)号：US20180006061A1

公开(公告)日：2018-01-04

申请号：US15708714

申请日：2017-09-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Okazaki ,  Tomoaki Moriwaka ,  Shinya Sasagawa ,  Takashi Ohtsuki

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/1255 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/7869

Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

公开(公告)号：US20240186331A1

公开(公告)日：2024-06-06

申请号：US18436245

申请日：2024-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka OKAZAKI ,  Tomoaki Moriwaka ,  Shinya Sasagawa ,  Takashi Ohtsuki

IPC: H01L27/12 ,  H01L21/768 ,  H01L23/532 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L21/76849 ,  H01L27/1255 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/7869 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266

Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

公开(公告)号：US11901372B2

公开(公告)日：2024-02-13

申请号：US18125426

申请日：2023-03-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Okazaki ,  Tomoaki Moriwaka ,  Shinya Sasagawa ,  Takashi Ohtsuki

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L27/124 ,  H01L21/76849 ,  H01L27/1255 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/78654 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266

Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

公开(公告)号：US09773820B2

公开(公告)日：2017-09-26

申请号：US14870912

申请日：2015-09-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Okazaki ,  Tomoaki Moriwaka ,  Shinya Sasagawa ,  Takashi Ohtsuki

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/1255 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/7869

Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

公开(公告)号：US09478664B2

公开(公告)日：2016-10-25

申请号：US14575052

申请日：2014-12-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Akihisa Shimomura ,  Yasumasa Yamane ,  Yuhei Sato ,  Tetsuhiro Tanaka ,  Masashi Tsubuku ,  Toshihiko Takeuchi ,  Ryo Tokumaru ,  Mitsuhiro Ichijo ,  Satoshi Toriumi ,  Takashi Ohtsuki ,  Toshiya Endo

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. The semiconductor device includes an oxide semiconductor film over an insulating surface, an antioxidant film over the insulating surface and the oxide semiconductor film, a pair of electrodes in contact with the antioxidant film, a gate insulating film over the pair of electrodes, and a gate electrode which is over the gate insulating film and overlaps with the oxide semiconductor film. In the antioxidant film, a width of a region overlapping with the pair of electrodes is longer than a width of a region not overlapping with the pair of electrodes.

Abstract translation: 抑制了电特性的变化，并且提高了使用包括氧化物半导体的晶体管的半导体器件的可靠性。 半导体器件包括绝缘表面上的氧化物半导体膜，绝缘表面上的抗氧化膜和氧化物半导体膜，与抗氧化膜接触的一对电极，一对电极上的栅极绝缘膜，以及栅极 电极，其在栅极绝缘膜上方并与氧化物半导体膜重叠。 在抗氧化剂膜中，与该对电极重叠的区域的宽度比不与该对电极重叠的区域的宽度长。