公开(公告)号：US20180144813A1

公开(公告)日：2018-05-24

申请号：US15632606

申请日：2017-06-26

Applicant: SK hynix Inc.

Inventor： Yong Hwan HONG ,  Byung Ryul KIM

IPC: G11C29/44 ,  G11C29/56 ,  G11C29/26 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C29/44 ,  G11C16/04 ,  G11C16/349 ,  G11C29/26 ,  G11C29/52 ,  G11C29/56 ,  G11C2029/0409 ,  G11C2029/1204

Abstract: Provided herein is a fail bit counter. The fail bit counter includes a pass/fail data receiver receiving pass/fail data indicating whether memory cells coupled to a bit line sequentially pass or fail, and a fail bit accumulator receiving a fail bit generation signal from the pass/fail data receiver, and accumulating and counting fail bits which are generated.

公开(公告)号：US20240168634A1

公开(公告)日：2024-05-23

申请号：US18295852

申请日：2023-04-05

Applicant: SK hynix Inc.

Inventor： Hyeok Chan SOHN ,  Byung Ryul KIM ,  Yong Soon PARK ,  Kang Wook JO

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0634 ,  G06F3/0679

Abstract: A memory device comprises a command decoding unit configured to generate a command by decoding an input signal applied to a first pad, wherein whether the command decoding unit is to be disabled is selected based on whether an operating state signal is activated, an operating state control unit configured to activate or deactivate the operating state signal in response to a set signal applied to the first pad, and an internal operation execution unit configured to perform a set internal operation in response to the command.

公开(公告)号：US20210182144A1

公开(公告)日：2021-06-17

申请号：US16856866

申请日：2020-04-23

Applicant: SK hynix Inc.

Inventor： Tae Ho LEE ,  Byung Ryul KIM ,  Dae Il CHOI ,  Yong Hwan HONG

IPC: G06F11/10 ,  G06F12/02 ,  G06F12/0882 ,  G06F9/30

Abstract: The present technology relates to a memory device, a memory system including the same, and a method of operating the memory system. The memory device includes a cam block including a plurality of pages, peripheral circuits configured to read a cam data of a page unit that is stored in a selected page among the plurality of pages of the cam block during a cam data read operation, a cam data read controller configured to receive the read cam data of the page unit from the peripheral circuits during a cam data load operation and configured to output the received cam data of the page unit as output cam data, and a control logic configured to control the peripheral circuits to perform the cam data read operation and the cam data load operation. The cam data read controller stops the cam data load operation based on a check data that is included in the read cam data of the page unit.

公开(公告)号：US20190035468A1

公开(公告)日：2019-01-31

申请号：US15858394

申请日：2017-12-29

Applicant: SK hynix Inc.

Inventor： Eun Kyu IN ,  Jae Woo PARK ,  Seok Won PARK ,  Byung Ryul KIM

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/32

Abstract: A memory device prevents generation of an abnormal column address. The memory device includes: a memory cell array; and a column address controller configured to generate a column address of the memory cell array in response to a column address control signal, wherein the column address controller enables the column address control signal when an address signal is input, and wherein the address signal includes a column address signal corresponding to the column address.

公开(公告)号：US20180067693A1

公开(公告)日：2018-03-08

申请号：US15582175

申请日：2017-04-28

Applicant: SK hynix Inc.

Inventor： Yong Hwan HONG ,  Byung Ryul KIM

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0688

Abstract: The invention relates to a memory device and a memory system having the same. The memory device includes a memory block including a plurality of pages, a peripheral circuit including a plurality of buffers sensing data stored in a selected page of the plurality of pages, temporarily storing high usage frequency data, and outputting the data, and a control circuit controlling the peripheral circuit to output the data after performing a sensing operation on the selected page, storing the high usage frequency data to at least one of the buffers, or outputting the high usage frequency data without performing the sensing operation in response to a read command.

公开(公告)号：US20220066685A1

公开(公告)日：2022-03-03

申请号：US17147996

申请日：2021-01-13

Applicant: SK hynix Inc.

Inventor： Yong Hwan HONG ,  Byung Ryul KIM

IPC: G06F3/06

Abstract: According to an embodiment, a semiconductor memory device includes a plurality of memory blocks including first to m-th guarantee blocks, wherein m is an integer greater than 1; repair logic suitable for generating bad block information by detecting defective memory blocks among the first to m-th guarantee blocks, and determining first to m-th offset values respectively corresponding to the first to m-th guarantee blocks based on the bad block information; and an address decoder suitable for generating a block selection address by reflecting an offset value selected from the first to m-th offset values onto a block address when the block address corresponds to any of the first to m-th guarantee blocks, and by reflecting the m-th offset value onto the block address when the block address corresponds to any of the memory blocks except for the first to m-th guarantee blocks.

公开(公告)号：US20190237153A1

公开(公告)日：2019-08-01

申请号：US16123514

申请日：2018-09-06

Applicant: SK hynix Inc.

Inventor： Yong Hwan HONG ,  Byung Ryul KIM

IPC: G11C29/44 ,  G11C16/04 ,  G11C29/18 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor memory device includes a memory cell array, a read/write circuit, and a control logic. The memory cell array includes a plurality of memory blocks. The read/write circuit performs a read/write operation on a selected page of the memory cell array. The address decoder stores bad block marking data on each of the plurality of memory blocks, and outputs the bad block marking data in response to an address signal. The control logic controls the read/write circuit to test whether a defect has occurred in the plurality of memory blocks, and controls the address decoder to store, as the bad block marking data, a test result representing whether the defect has occurred in the plurality of memory blocks.

公开(公告)号：US20240302992A1

公开(公告)日：2024-09-12

申请号：US18670027

申请日：2024-05-21

Applicant: SK hynix Inc.

Inventor： Hyeok Chan SOHN ,  Kang Wook JO ,  Hyeon Cheon SEOL ,  Byung Ryul KIM ,  Jae Young LEE

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0608 ,  G06F3/0679

Abstract: A storage device may include: a memory device for extracting bits having a first logic value among bits included in data received from outside the memory device, generating a plurality of compressed data chunks including the bits comprising the first logic value and position information representing positions of the bits having the first logic value in the data, and outputting the plurality of compressed data chunks in response to a data output command; and a memory controller for receiving the plurality of compressed data chunks from the memory device, and recovering the data, based on the bits having the first logic value, which are included in the plurality of compressed data, and the position information.

公开(公告)号：US20240185929A1

公开(公告)日：2024-06-06

申请号：US18325730

申请日：2023-05-30

Applicant: SK hynix Inc.

Inventor： Hyeok Chan SOHN ,  Beom Ju SHIN ,  Byung Ryul KIM ,  Kang Wook JO

IPC: G11C16/26 ,  G11C16/12

CPC classification number: G11C16/26 ,  G11C16/12

Abstract: The present technology relates to an electronic device. A memory device according to the present technology may include a first plane, a second plane, a data input/output circuit, and an encoder. The data input/output circuit may output data read from the first and second planes. The encoder may compress second data read from the second plane while first data read from the first plane is being output. The data input/output circuit may output the compressed second data after outputting the first data.

公开(公告)号：US20220270694A1

公开(公告)日：2022-08-25

申请号：US17383174

申请日：2021-07-22

Applicant: SK hynix Inc.

Inventor： Jae Young LEE ,  Yong Hwan HONG ,  Byung Ryul KIM

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C29/44 ,  G11C7/10

Abstract: A memory device includes a memory block including a plurality of pages, a peripheral circuit configured to perform a first program operation for storing first page data and a second program operation for storing second page data after the first program operation, a status register configured to store status information, a cache program operation controller configured to control the peripheral circuit to load the second page data from an external controller when the first program operation is being performed, and a status register controller configured to store in the status register first failure information indicating whether the first program operation passes, store in the status register validity information indicating whether the first failure information is valid information within a predetermined time period from when the second program operation starts, and provide the external controller with the status information including the first failure information and the validity information.