公开(公告)号：US20130078807A1

公开(公告)日：2013-03-28

申请号：US13680668

申请日：2012-11-19

Applicant: SK HYNIX INC.

Inventor： Chang Jun PARK ,  Kwon Whan HAN ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE ,  Tac Keun OH ,  Sang Joon LIM

IPC: H01L21/48

CPC classification number: H01L21/486 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

Abstract: A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

公开(公告)号：US20190259743A1

公开(公告)日：2019-08-22

申请号：US16176806

申请日：2018-10-31

Applicant: SK hynix Inc.

Inventor： Kwon Whan HAN

IPC: H01L25/00 ,  H01L25/18 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48

Abstract: A method of fabricating semiconductor packages may include forming stack structures on a base die wafer, disposing a top die wafer on the stack structures, and forming a molding layer filling a space between the base die wafer and the top die wafer.

公开(公告)号：US20140014958A1

公开(公告)日：2014-01-16

申请号：US13737394

申请日：2013-01-09

Applicant: SK HYNIX INC.

Inventor： Tac Keun OH ,  Jae Sung OH ,  Kwon Whan HAN ,  Woong Sun LEE ,  Seon Kwang JEON

IPC: H01L21/66

CPC classification number: H01L22/00 ,  H01L22/32 ,  H01L23/481 ,  H01L23/5256 ,  H01L23/5258 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06565

Abstract: A semiconductor chip module includes a first semiconductor chip having first through-electrodes, a second semiconductor chip having second through-electrodes which are electrically connected with the first through-electrodes, first and second test pads, a first connection line which connects the first test pad with one second through-electrode, a second connection line which connects the second test pad with another second through-electrode, third connection lines which connect the remaining second through-electrodes into pairs, and are partially constituted by fuses, and a third semiconductor chip having fourth connection lines which electrically connect the first through-electrodes of the first semiconductor chip into pairs, wherein the first and second is through-electrodes are connected in series between the first test pad and the second test pad by the first connection line, the second connection line, the third connection lines, and the fourth connection lines.

Abstract translation: 半导体芯片模块包括具有第一通孔的第一半导体芯片，具有与第一通孔电连接的第二贯通电极的第二半导体芯片，第一和第二测试焊盘，连接第一测试 具有一个第二贯通电极的焊盘，连接第二测试焊盘与另一个第二贯通电极的第二连接线，将剩余的第二贯通电极成对连接并部分地由保险丝构成的第三连接线，以及第三半导体 芯片具有将第一半导体芯片的第一贯通电极电连接成对的第四连接线，其中，第一和第二直通电极通过第一连接线串联连接在第一测试焊盘和第二测试焊盘之间， 第二连接线，第三连接线和第四连接线。