公开(公告)号：US20130292844A1

公开(公告)日：2013-11-07

申请号：US13693458

申请日：2012-12-04

Applicant: SK HYNIX INC.

Inventor： Tac Keun OH

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/45139 ,  H01L2224/48227 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor package includes a first interposer; first and second semiconductor chips horizontally mounted over the first interposer and electrically connected with the first interposer; and a second interposer disposed over the first and second semiconductor chips and electrically connected with the first and second semiconductor chips, wherein the first semiconductor chip includes a plurality of first through electrodes, and the second semiconductor chip includes a plurality of second through electrodes, and wherein the first through electrodes of the first semiconductor chip and the second through electrodes of the second semiconductor chip are electrically connected with each other through the first and second interposers.

Abstract translation: 半导体封装包括第一插入件; 第一和第二半导体芯片水平安装在第一插入件上并与第一插入件电连接; 以及设置在所述第一和第二半导体芯片上并与所述第一和第二半导体芯片电连接的第二插入件，其中所述第一半导体芯片包括多个第一贯穿电极，并且所述第二半导体芯片包括多个第二贯通电极，以及 其中，所述第一半导体芯片的所述第一贯通电极和所述第二半导体芯片的所述第二贯通电极通过所述第一和第二插入件彼此电连接。

公开(公告)号：US20170287734A1

公开(公告)日：2017-10-05

申请号：US15629007

申请日：2017-06-21

Applicant: SK hynix Inc.

Inventor： Tac Keun OH ,  Seung Taek YANG

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/81005 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2224/81

Abstract: A semiconductor package may include a semiconductor die mounted on a first surface of an interposer die so that a die connection portion of the semiconductor die faces to the first surface of the interposer die, a protection portion may be disposed on the first surface of the interposer die to cover the semiconductor die, and an interconnection structure disposed in and on the interposer die. The interconnection structure may include an external connection portion that is located on a second surface of the interposer die opposite to the semiconductor die, a through electrode portion that penetrates the interposer die to have an end portion combined with the die connection portion, and an extension portion that connects the through electrode portion to the external connection portion. Related methods are also provided.

公开(公告)号：US20150061120A1

公开(公告)日：2015-03-05

申请号：US14189876

申请日：2014-02-25

Applicant: SK hynix Inc.

Inventor： Seung Taek YANG ,  Jong Hoon KIM ,  Tac Keun OH ,  Song NA

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83005 ,  H01L2224/83101 ,  H01L2224/83104 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/92224 ,  H01L2224/95 ,  H01L2224/96 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L21/56 ,  H01L2224/19 ,  H01L21/78 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83

Abstract: Embodiments of a stack package may include an upper chip on a lower chip, a backside passivation layer covering the backside surface of the lower chip and having a thickness which is substantially equal to a height of the protrusion portion of a lower through via electrode, a backside bump substantially contacting the protrusion portion, and a front side bump electrically connected to a chip contact portion of the upper chip and physically and electrically connected to the backside bump. The backside passivation layer may include a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip. Embodiments of fabrication methods are also disclosed.

Abstract translation: 堆叠封装的实施例可以包括下芯片上的上芯片，覆盖下芯片的背面的背面钝化层，其厚度基本上等于下通孔电极的突出部分的高度， 背面凸块基本上接触突出部分，以及电连接到上芯片的芯片接触部分并且物理和电连接到背侧凸块的前侧凸块。 背侧钝化层可以包括设置在突出部分的侧壁和下部芯片的背面上的第一绝缘层。 还公开了制造方法的实施例。

公开(公告)号：US20150311182A1

公开(公告)日：2015-10-29

申请号：US14461840

申请日：2014-08-18

Applicant: SK hynix Inc.

Inventor： Jeong Hwan LEE ,  Tac Keun OH

IPC: H01L25/065 ,  H01L23/373

CPC classification number: H01L23/3737 ,  H01L23/13 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/562 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511

Abstract: A semiconductor package may include an interposer; a first semiconductor chip disposed on a first surface of the interposer and at least one second semiconductor chip disposed at a predefined distance from the first semiconductor chip, a molding part filling spaces between the first semiconductor chip and the at least one second semiconductor chip and having a trench hole formed therein, and a thermal expansion buffer pattern filling the trench hole.

Abstract translation: 半导体封装可以包括中介层; 设置在所述插入件的第一表面上的第一半导体芯片和设置在距离所述第一半导体芯片预定距离的至少一个第二半导体芯片;模制部分，填充所述第一半导体芯片和所述至少一个第二半导体芯片之间的空间，并且具有 形成在其中的沟槽孔和填充沟槽孔的热膨胀缓冲图案。

公开(公告)号：US20130078807A1

公开(公告)日：2013-03-28

申请号：US13680668

申请日：2012-11-19

Applicant: SK HYNIX INC.

Inventor： Chang Jun PARK ,  Kwon Whan HAN ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE ,  Tac Keun OH ,  Sang Joon LIM

IPC: H01L21/48

CPC classification number: H01L21/486 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

Abstract: A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

公开(公告)号：US20160379845A1

公开(公告)日：2016-12-29

申请号：US14957845

申请日：2015-12-03

Applicant: SK hynix Inc.

Inventor： Tac Keun OH ,  Seung Taek YANG

IPC: H01L21/48 ,  H01L21/56

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/81005 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2224/81

Abstract: A semiconductor package may include a semiconductor die mounted on a first surface of an interposer die so that a die connection portion of the semiconductor die faces to the first surface of the interposer die, a protection portion may be disposed on the first surface of the interposer die to cover the semiconductor die, and an interconnection structure disposed in and on the interposer die. The interconnection structure may include an external connection portion that is located on a second surface of the interposer die opposite to the semiconductor die, a through electrode portion that penetrates the interposer die to have an end portion combined with the die connection portion, and an extension portion that connects the through electrode portion to the external connection portion. Related methods are also provided.

Abstract translation: 半导体封装可以包括安装在插入器管芯的第一表面上的半导体管芯，使得半导体管芯的管芯连接部分面向插入器管芯的第一表面，保护部分可以设置在插入件的第一表面上 模具以覆盖半导体管芯，以及布置在插入件裸片中和插入件裸片上的互连结构。 互连结构可以包括位于与半导体管芯相对的插入件管芯的第二表面上的外部连接部分，穿过插入器管芯以使端部与管芯连接部分结合的通孔部分，以及延伸部 将通电极部与外部连接部连接的部分。 还提供了相关方法。

公开(公告)号：US20150340303A1

公开(公告)日：2015-11-26

申请号：US14460734

申请日：2014-08-15

Applicant: SK HYNIX INC.

Inventor： Tac Keun OH ,  Jong Hoon KIM ,  Ho Young SON ,  Jeong Hwan LEE

IPC: H01L23/36 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/36 ,  H01L21/486 ,  H01L21/4871 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/42 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A multi chip package includes a protective layer having an upper surface that surrounds a first chip and a second chip, which are mounted over a first substrate, to expose an upper surface of the first chip and an upper surface of the second chip, a heat spreader disposed over the upper surfaces, and a thermal interface material disposed at an interface between the heat spreader and the upper surfaces.

Abstract translation: 一种多芯片封装，包括具有包围第一芯片的上表面的保护层和安装在第一基板上的第二芯片，以暴露第一芯片的上表面和第二芯片的上表面，热量 布置在上表面上的扩散器，以及设置在散热器和上表面之间的界面处的热界面材料。

公开(公告)号：US20150303181A1

公开(公告)日：2015-10-22

申请号：US14466921

申请日：2014-08-22

Applicant: SK Hynix Inc.

Inventor： Jong Hoon KIM ,  Tac Keun OH ,  Jeong Hwan LEE

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5386 ,  H01L23/562 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00

Abstract: A semiconductor package includes an interposer, first and second semiconductor chips horizontally arranged over a first surface of the interposer, the second semiconductor chip being adjacent to the first semiconductor chip, and a thermal expansion reinforcing pattern disposed over a second surface of the interposer.

Abstract translation: 半导体封装包括插入件，水平地布置在插入件的第一表面上的第一和第二半导体芯片，与第一半导体芯片相邻的第二半导体芯片，以及设置在插入件的第二表面上的热膨胀增强图案。

公开(公告)号：US20140335656A1

公开(公告)日：2014-11-13

申请号：US14337905

申请日：2014-07-22

Applicant: SK hynix Inc.

Inventor： Tac Keun OH

IPC: H01L25/00

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L23/3135 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/29099 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/80203 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: Semiconductor chip stacks are provided. The semiconductor chip stack includes a semiconductor chip stack including a plurality of first semiconductor chips vertically stacked on a top surface of the interposer, a second semiconductor chip stacked on a bottom surface of the interposer opposite to the semiconductor chip stack, and an external electrode attached to a top surface of the second semiconductor chip opposite to the interposer. Electronic systems including the semiconductor chip stack and related methods are also provided.

Abstract translation: 提供半导体芯片堆叠。 半导体芯片堆叠包括：半导体芯片堆叠，包括垂直堆叠在插入件的顶表面上的多个第一半导体芯片，堆叠在与半导体芯片堆叠体相反的插入器的底表面上的第二半导体芯片，以及外部电极 到达与内插器相对的第二半导体芯片的顶表面。 还提供了包括半导体芯片堆叠和相关方法的电子系统。

公开(公告)号：US20140014958A1

公开(公告)日：2014-01-16

申请号：US13737394

申请日：2013-01-09

Applicant: SK HYNIX INC.

Inventor： Tac Keun OH ,  Jae Sung OH ,  Kwon Whan HAN ,  Woong Sun LEE ,  Seon Kwang JEON

IPC: H01L21/66

CPC classification number: H01L22/00 ,  H01L22/32 ,  H01L23/481 ,  H01L23/5256 ,  H01L23/5258 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06565

Abstract: A semiconductor chip module includes a first semiconductor chip having first through-electrodes, a second semiconductor chip having second through-electrodes which are electrically connected with the first through-electrodes, first and second test pads, a first connection line which connects the first test pad with one second through-electrode, a second connection line which connects the second test pad with another second through-electrode, third connection lines which connect the remaining second through-electrodes into pairs, and are partially constituted by fuses, and a third semiconductor chip having fourth connection lines which electrically connect the first through-electrodes of the first semiconductor chip into pairs, wherein the first and second is through-electrodes are connected in series between the first test pad and the second test pad by the first connection line, the second connection line, the third connection lines, and the fourth connection lines.

Abstract translation: 半导体芯片模块包括具有第一通孔的第一半导体芯片，具有与第一通孔电连接的第二贯通电极的第二半导体芯片，第一和第二测试焊盘，连接第一测试 具有一个第二贯通电极的焊盘，连接第二测试焊盘与另一个第二贯通电极的第二连接线，将剩余的第二贯通电极成对连接并部分地由保险丝构成的第三连接线，以及第三半导体 芯片具有将第一半导体芯片的第一贯通电极电连接成对的第四连接线，其中，第一和第二直通电极通过第一连接线串联连接在第一测试焊盘和第二测试焊盘之间， 第二连接线，第三连接线和第四连接线。