公开(公告)号：US20240355376A1

公开(公告)日：2024-10-24

申请号：US18454449

申请日：2023-08-23

Applicant: SK hynix Inc.

Inventor： Jae Hyeong HONG ,  In Seok KONG ,  Bon Kwang KOO ,  Gwan Woo KIM ,  Heon Ki KIM ,  Beom Kyu SEO ,  Keun Seon AHN ,  Soon Sung AN ,  Sung Hwa OK ,  Jung Yeop LEE ,  Ji Young LEE ,  Dong Wook JANG ,  Jun Seo JANG ,  Sun Ki CHO ,  Eun Ji CHOI

IPC: G11C11/4074 ,  G11C16/26

CPC classification number: G11C11/4074 ,  G11C16/26

Abstract: A voltage generation circuit includes a voltage generation unit configured to generate a reference voltage using a power supply voltage and output the reference voltage through a voltage output node. The voltage generation circuit also includes a pre-charge unit configured to drive the voltage output node using the power supply voltage in response to a pre-charge control signal. The voltage generation circuit further includes a pre-charge control unit configured to generate at least one sampling voltage using the power supply voltage and generate the pre-charge control signal according to a result obtained by comparing the at least one sampling voltage with the reference voltage.

公开(公告)号：US20170019107A1

公开(公告)日：2017-01-19

申请号：US15047864

申请日：2016-02-19

Applicant: SK hynix Inc.

Inventor： Sun Ki CHO

IPC: H03K19/0185

CPC classification number: H03K19/018521

Abstract: A semiconductor apparatus may include a transmission circuit, a reception circuit, and a pad commonly coupled to the transmission circuit and the reception circuit. When either the transmission circuit or the reception circuit is activated, parasitic capacitance of a line coupled to the transmission circuit, the reception circuit, and the pad is varied.

Abstract translation: 半导体装置可以包括传输电路，接收电路和共同耦合到传输电路和接收电路的焊盘。 当传输电路或接收电路都被激活时，耦合到传输电路，接收电路和焊盘的线路的寄生电容变化。

公开(公告)号：US20140062557A1

公开(公告)日：2014-03-06

申请号：US13720992

申请日：2012-12-19

Applicant: SK HYNIX INC.

Inventor： Sung Woo HAN ,  Ic Su OH ,  Jun Ho LEE ,  Boo Ho JUNG ,  Sun Ki CHO ,  Yang Hee KIM ,  Tae Hoon KIM

IPC: H03K5/12

CPC classification number: H03K3/013 ,  G06F17/5022 ,  H03K5/12

Abstract: Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result.

Abstract translation: 提供了一种减少包括多个输出缓冲器以输出数据的半导体装置的输出数据噪声的方法。 该方法包括以下步骤：将低数据驱动到多个输出缓冲器中的特定输出缓冲器，以及驱动数据从高电平转移到低电平到另一个输出缓冲器; 以及测量在特定输出缓冲器的输出数据中发生的数据噪声的大小，以及基于测量结果确定多个输出缓冲器的转换速率。

公开(公告)号：US20190356289A1

公开(公告)日：2019-11-21

申请号：US16209650

申请日：2018-12-04

Applicant: SK hynix Inc.

Inventor： Sun Ki CHO ,  Dae Han KWON

IPC: H03F3/45 ,  H03F3/72 ,  H04L25/02

Abstract: A receiving circuit may include an amplifier. The amplifier may include a first amplification circuit and a second amplification circuit. The first amplification circuit may be configured to differentially amplify a first input signal and a reference signal and configured to generate output signals. The second amplification circuit may be configured to differentially amplify a second input signal and the reference signal and configured to generate the output signals.

公开(公告)号：US20170345474A1

公开(公告)日：2017-11-30

申请号：US15286722

申请日：2016-10-06

Applicant: SK hynix Inc.

Inventor： Kyung Hoon KIM ,  Sun Ki CHO

IPC: G11C8/18 ,  G11C7/12 ,  G11C7/10

CPC classification number: G11C8/18 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/12

Abstract: A transmission circuit may be provided. The transmission circuit may include a strobe control circuit and an output driver. The strobe control circuit may generate strobe driving signals based on information and a clock signal. The output driver may generate a strobe signal by driving a signal transmission line. The transmission circuit may drive the signal transmission line to a specified level for a predetermined time after transmission of the strobe signal is completed.

公开(公告)号：US20150109041A1

公开(公告)日：2015-04-23

申请号：US14581357

申请日：2014-12-23

Applicant: SK hynix Inc.

Inventor： Sung Woo HAN ,  Ic Su OH ,  Jun Ho LEE ,  Boo Ho JUNG ,  Sun Ki CHO ,  Yang Hee KIM ,  Tae Hoon KIM

IPC: H03K3/013 ,  H03K5/12

CPC classification number: H03K3/013 ,  G06F17/5022 ,  H03K5/12

Abstract: Provided is a semiconductor apparatus which includes a plurality of output buffers configured to connect a plurality of power sources, and a data noise measuring unit configured to fix an output data of a selected output buffer among the plurality of output buffers to have a specific level, measure a noise of the output data using a capacitance and control a slew rate of the plurality of output buffers based on the noise.

Abstract translation: 提供了一种半导体装置，其包括多个输出缓冲器，其被配置为连接多个电源;以及数据噪声测量单元，被配置为将所述多个输出缓冲器中的所选输出缓冲器的输出数据固定为具有特定电平， 使用电容测量输出数据的噪声，并基于噪声控制多个输出缓冲器的转换速率。

公开(公告)号：US20140140016A1

公开(公告)日：2014-05-22

申请号：US13845568

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Jun Ho LEE ,  Sung Woo HAN ,  Ic Su OH ,  Boo Ho JUNG ,  Sun Ki CHO ,  Yang Hee KIM ,  Tae Hoon KIM

IPC: H03H7/01 ,  H05K1/18

CPC classification number: H03H7/0115 ,  G11C5/14 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5286 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6661 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power metal mesh and a semiconductor memory device including the same are provided. As the power metal mesh configured to reduce noise coupling generated between adjacent chips disposed on an interposer, a band stop filter unit including an inductor and a capacitor coupled in parallel is disposed between the adjacent chips to effectively reduce the noise coupling of a specific frequency band generated between the adjacent chips.

Abstract translation: 提供了一种功率金属网和包括其的半导体存储器件。 由于功率金属网被配置为减少在设置在插入器上的相邻芯片之间产生的噪声耦合，所以包括电感器和并联的电容器的带阻滤波器单元设置在相邻芯片之间，以有效地减小特定频带的噪声耦合 在相邻芯片之间产生。

公开(公告)号：US20250079361A1

公开(公告)日：2025-03-06

申请号：US18428240

申请日：2024-01-31

Applicant: SK hynix Inc.

Inventor： Yang Ho SUR ,  Sun Ki CHO

IPC: H01L23/00

Abstract: An external connection pad apparatus includes a first pad and a second pad. The first pad has a first surface area. The second pad has a second surface area larger than the first surface area.

公开(公告)号：US20240413814A1

公开(公告)日：2024-12-12

申请号：US18810138

申请日：2024-08-20

Applicant: SK hynix Inc.

Inventor： Sun Ki CHO ,  Yang Ho SUR ,  Ic Su OH

IPC: H03K5/01 ,  H03K5/00

Abstract: An oscillating signal generating circuit drives an oscillating signal to a first logic level based on a first control signal, which is generated by delaying the oscillating signal through a clock delaying circuit, and drives the oscillating signal to a second logic level based on a second control signal, which is generated by delaying the oscillating signal by a fixed delay amount.

公开(公告)号：US20230336166A1

公开(公告)日：2023-10-19

申请号：US17899030

申请日：2022-08-30

Applicant: SK hynix Inc.

Inventor： Sun Ki CHO ,  Yang Ho SUR ,  Ic Su OH

IPC: H03K5/01

CPC classification number: H03K5/01 ,  H03K2005/00078

Abstract: An oscillating signal generating circuit drives an oscillating signal to a first logic level based on a first control signal, which is generated by delaying the oscillating signal through a clock delaying circuit, and drives the oscillating signal to a second logic level based on a second control signal, which is generated by delaying the oscillating signal by a fixed delay amount.