公开(公告)号：US20160104684A1

公开(公告)日：2016-04-14

申请号：US14960716

申请日：2015-12-07

Applicant: SK hynix Inc.

Inventor： Chang Kun PARK ,  Seong Hwi SONG ,  Yong Ju KIM ,  Sung Woo HAN ,  Hee Woong SONG ,  Ic Su OH ,  Hyung Soo KIM ,  Tae Jin HWANG ,  Hae Rang CHOI ,  Ji Wang LEE ,  Jae Min JANG

IPC: H01L23/00 ,  H01L23/528

CPC classification number: H01L24/06 ,  H01L23/5286 ,  H01L24/09 ,  H01L27/1052 ,  H01L2224/061 ,  H01L2224/0612 ,  H01L2224/06515 ,  H01L2224/091 ,  H01L2224/09515 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/30101 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

公开(公告)号：US20240413814A1

公开(公告)日：2024-12-12

申请号：US18810138

申请日：2024-08-20

Applicant: SK hynix Inc.

Inventor： Sun Ki CHO ,  Yang Ho SUR ,  Ic Su OH

IPC: H03K5/01 ,  H03K5/00

Abstract: An oscillating signal generating circuit drives an oscillating signal to a first logic level based on a first control signal, which is generated by delaying the oscillating signal through a clock delaying circuit, and drives the oscillating signal to a second logic level based on a second control signal, which is generated by delaying the oscillating signal by a fixed delay amount.

公开(公告)号：US20230336166A1

公开(公告)日：2023-10-19

申请号：US17899030

申请日：2022-08-30

Applicant: SK hynix Inc.

Inventor： Sun Ki CHO ,  Yang Ho SUR ,  Ic Su OH

IPC: H03K5/01

CPC classification number: H03K5/01 ,  H03K2005/00078

Abstract: An oscillating signal generating circuit drives an oscillating signal to a first logic level based on a first control signal, which is generated by delaying the oscillating signal through a clock delaying circuit, and drives the oscillating signal to a second logic level based on a second control signal, which is generated by delaying the oscillating signal by a fixed delay amount.

公开(公告)号：US20140062557A1

公开(公告)日：2014-03-06

申请号：US13720992

申请日：2012-12-19

Applicant: SK HYNIX INC.

Inventor： Sung Woo HAN ,  Ic Su OH ,  Jun Ho LEE ,  Boo Ho JUNG ,  Sun Ki CHO ,  Yang Hee KIM ,  Tae Hoon KIM

IPC: H03K5/12

CPC classification number: H03K3/013 ,  G06F17/5022 ,  H03K5/12

Abstract: Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result.

Abstract translation: 提供了一种减少包括多个输出缓冲器以输出数据的半导体装置的输出数据噪声的方法。 该方法包括以下步骤：将低数据驱动到多个输出缓冲器中的特定输出缓冲器，以及驱动数据从高电平转移到低电平到另一个输出缓冲器; 以及测量在特定输出缓冲器的输出数据中发生的数据噪声的大小，以及基于测量结果确定多个输出缓冲器的转换速率。

公开(公告)号：US20160218713A1

公开(公告)日：2016-07-28

申请号：US14697916

申请日：2015-04-28

Applicant: SK hynix Inc.

Inventor： Ic Su OH ,  Chang Kyu CHOI ,  Dae Han KWON

IPC: H03K19/00 ,  H03K19/0185 ,  H03K3/356

CPC classification number: H03K19/0013 ,  H03K3/356104 ,  H03K3/35613 ,  H03K3/356165 ,  H03K19/018521 ,  H03K19/018571 ,  H03K19/018585

Abstract: A semiconductor device is disclosed, which relates to a technology for reducing current consumption of a semiconductor chip configured to operate a transmitter (Tx) at a high speed. The semiconductor device includes a data driving unit configured to output a pull-up drive signal and a pull-down drive signal by level-shifting an input signal according to a clock signal; and a data output unit configured to adjust slew rates of the pull-up drive signal and the pull-down drive signal according to a code signal, and output impedance-adjusted signals to an output terminal.

Abstract translation: 公开了一种半导体器件，其涉及用于降低被配置为以高速操作发射器（Tx）的半导体芯片的电流消耗的技术。 半导体器件包括：数据驱动单元，被配置为通过根据时钟信号对输入信号进行电平移位来输出上拉驱动信号和下拉驱动信号; 以及数据输出单元，被配置为根据代码信号调整上拉驱动信号和下拉驱动信号的转换速率，并将阻抗调整信号输出到输出端子。

公开(公告)号：US20150109041A1

公开(公告)日：2015-04-23

申请号：US14581357

申请日：2014-12-23

Applicant: SK hynix Inc.

Inventor： Sung Woo HAN ,  Ic Su OH ,  Jun Ho LEE ,  Boo Ho JUNG ,  Sun Ki CHO ,  Yang Hee KIM ,  Tae Hoon KIM

IPC: H03K3/013 ,  H03K5/12

CPC classification number: H03K3/013 ,  G06F17/5022 ,  H03K5/12

Abstract: Provided is a semiconductor apparatus which includes a plurality of output buffers configured to connect a plurality of power sources, and a data noise measuring unit configured to fix an output data of a selected output buffer among the plurality of output buffers to have a specific level, measure a noise of the output data using a capacitance and control a slew rate of the plurality of output buffers based on the noise.

Abstract translation: 提供了一种半导体装置，其包括多个输出缓冲器，其被配置为连接多个电源;以及数据噪声测量单元，被配置为将所述多个输出缓冲器中的所选输出缓冲器的输出数据固定为具有特定电平， 使用电容测量输出数据的噪声，并基于噪声控制多个输出缓冲器的转换速率。

公开(公告)号：US20150076703A1

公开(公告)日：2015-03-19

申请号：US14550445

申请日：2014-11-21

Applicant: SK hynix Inc.

Inventor： Chang Kun PARK ,  Seong Hwi SONG ,  Yong Ju KIM ,  Sung Woo HAN ,  Hee Woong SONG ,  Ic Su OH ,  Hyung Soo KIM ,  Tae Jin HWANG ,  Hae Rang CHOI ,  Ji Wang LEE ,  Jae Min JANG

IPC: H01L23/00 ,  H01L27/105

CPC classification number: H01L24/06 ,  H01L23/5286 ,  H01L24/09 ,  H01L27/1052 ,  H01L2224/061 ,  H01L2224/0612 ,  H01L2224/06515 ,  H01L2224/091 ,  H01L2224/09515 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/30101 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

公开(公告)号：US20140140016A1

公开(公告)日：2014-05-22

申请号：US13845568

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Jun Ho LEE ,  Sung Woo HAN ,  Ic Su OH ,  Boo Ho JUNG ,  Sun Ki CHO ,  Yang Hee KIM ,  Tae Hoon KIM

IPC: H03H7/01 ,  H05K1/18

CPC classification number: H03H7/0115 ,  G11C5/14 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5286 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6661 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power metal mesh and a semiconductor memory device including the same are provided. As the power metal mesh configured to reduce noise coupling generated between adjacent chips disposed on an interposer, a band stop filter unit including an inductor and a capacitor coupled in parallel is disposed between the adjacent chips to effectively reduce the noise coupling of a specific frequency band generated between the adjacent chips.

Abstract translation: 提供了一种功率金属网和包括其的半导体存储器件。 由于功率金属网被配置为减少在设置在插入器上的相邻芯片之间产生的噪声耦合，所以包括电感器和并联的电容器的带阻滤波器单元设置在相邻芯片之间，以有效地减小特定频带的噪声耦合 在相邻芯片之间产生。

公开(公告)号：US20250125795A1

公开(公告)日：2025-04-17

申请号：US18597637

申请日：2024-03-06

Applicant: SK hynix Inc.

Inventor： Soon Chul KWON ,  Min Chang KIM ,  Seul Gi KIM ,  Hong Joo SONG ,  Ic Su OH

IPC: H03K5/02 ,  H03K3/037 ,  H03K5/00 ,  H03K5/135

Abstract: A phase mixer circuit is configured to receive a first input clock signal and a second input clock signal, and to generate an intermediate clock signal having an intermediate phase between phases of the first and second input clock signals. The phase mixer circuit is configured to determine a logic value of a mixed code signal, and to generate an output clock signal by mixing one of the first and second input clock signals and the intermediate clock signal.

公开(公告)号：US20150076614A1

公开(公告)日：2015-03-19

申请号：US14550328

申请日：2014-11-21

Applicant: SK hynix Inc.

Inventor： Chang Kun PARK ,  Seong Hwi SONG ,  Yong Ju KIM ,  Sung Woo HAN ,  Hee Woong SONG ,  Ic Su OH ,  Hyung Soo KIM ,  Tae Jin HWANG ,  Hae Rang CHOI ,  Ji Wang LEE ,  Jae Min JANG

IPC: H01L23/00 ,  H01L27/105

CPC classification number: H01L24/06 ,  H01L23/5286 ,  H01L24/09 ,  H01L27/1052 ,  H01L2224/061 ,  H01L2224/0612 ,  H01L2224/06515 ,  H01L2224/091 ,  H01L2224/09515 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/30101 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract translation: 半导体存储器件包括具有芯片焊盘形成区域的半导体电路基板。 在芯片焊盘区域一侧的半导体电路基板上形成一对数据线。 一对数据线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸。 这对数据线被布置为彼此相邻并且接收一对差分数据信号。 电源线形成在芯片焊盘区域的另一侧的半导体电路基板上。 电源线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸，并且电源线接收电力。