公开(公告)号：US09634102B2

公开(公告)日：2017-04-25

申请号：US15069282

申请日：2016-03-14

Applicant: SK hynix Inc.

Inventor： Tae Ho Lee

IPC: H01L29/788 ,  H01L29/417 ,  H01L27/11519 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/41758 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/788 ,  H01L29/7887

Abstract: A nonvolatile memory device includes a plurality of twin cells arrayed on a substrate. Each of the plurality of twin cells includes a drain mesa protruding from a surface of a substrate. A first source and a second source are disposed in the substrate and spaced apart from the drain mesa. A first floating gate overlaps with a first sidewall surface of the drain mesa and extends onto the first source, and a second floating gate overlaps with a second sidewall surface of the drain mesa and extends onto the second source. Related methods are also provided.

公开(公告)号：US09508733B1

公开(公告)日：2016-11-29

申请号：US14885371

申请日：2015-10-16

Applicant: SK hynix Inc.

Inventor： Tae Ho Lee ,  Young Joon Kwon ,  Sung Kun Park

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L21/265 ,  H01L21/266 ,  H01L29/51

CPC classification number: H01L29/518 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66833

Abstract: A method of fabricating an embedded electronic device including charge trap memory cells that includes forming a tunnel insulation layer, a charge trap layer and a sacrificial insulation layer on a substrate having a first region and a second region. The tunnel insulation layer, the charge trap layer and the sacrificial insulation layer which are stacked on the second region of the substrate are selectively removed. A well region is formed in an upper region of the second region of the substrate. The sacrificial insulation layer remaining over the first region is removed to expose the charge trap layer remaining over the first region. A blocking insulation layer and a gate insulation layer are formed on the exposed charge trap layer over the first region and on the second region of the substrate, respectively.

Abstract translation: 一种制造包括电荷陷阱存储单元的嵌入式电子器件的方法，包括在具有第一区域和第二区域的衬底上形成隧道绝缘层，电荷陷阱层和牺牲绝缘层。 选择性地去除层叠在基板的第二区域上的隧道绝缘层，电荷陷阱层和牺牲绝缘层。 阱区域形成在衬底的第二区域的上部区域中。 残留在第一区域上的牺牲绝缘层被去除以暴露残留在第一区域上的电荷陷阱层。 分别在基板的第一区域和第二区域上的暴露的电荷陷阱层上形成隔离绝缘层和栅极绝缘层。

公开(公告)号：US09412690B2

公开(公告)日：2016-08-09

申请号：US14325081

申请日：2014-07-07

Applicant: SK HYNIX INC.

Inventor： Tae Ho Lee ,  Il Hwan Cho ,  In Chul Hwang ,  Ga Hyun No

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A package substrate includes a substrate body and a plurality of patterns disposed on the substrate body. The substrate body has a first region including a chip attachment region and a second region adjacent to the first region. The plurality of patterns are disposed on the substrate body in the second region. Each of the plurality of patterns extends in a first direction to have a stripe shape, and the plurality of patterns are spaced apart from each other in a second direction which is substantially perpendicular to the first direction. Related fabrication methods, electronic systems and memory cards are also provided.

Abstract translation: 封装基板包括基板主体和布置在基板主体上的多个图案。 基板主体具有包括芯片附接区域和与第一区域相邻的第二区域的第一区域。 多个图案设置在第二区域中的基板主体上。 多个图案中的每一个在第一方向上延伸以具有条形形状，并且多个图案在基本上垂直于第一方向的第二方向上彼此间隔开。 还提供了相关的制造方法，电子系统和存储卡。

公开(公告)号：US11132252B2

公开(公告)日：2021-09-28

申请号：US16856866

申请日：2020-04-23

Applicant: SK hynix Inc.

Inventor： Tae Ho Lee ,  Byung Ryul Kim ,  Dae Il Choi ,  Yong Hwan Hong

IPC: G06F11/00 ,  G06F11/10 ,  G06F9/30 ,  G06F12/0882 ,  G06F12/02

Abstract: The memory device includes a content addressable memory (CAM) block including a plurality of pages, peripheral circuits configured to perform a CAM data read operation to read a CAM data comprising a plurality of check data each indicating whether bad block information is included in a region of the CAM data from a page sequentially selected among the plurality of pages, a CAM data read controller configured to perform a CAM data load operation to receive the CAM data from the peripheral circuits and output the CAM data to an external memory controller, and stop the CAM data load operation based on at least one check data among the plurality of check data included in the CAM data.

公开(公告)号：US09318497B2

公开(公告)日：2016-04-19

申请号：US14470652

申请日：2014-08-27

Applicant: SK hynix Inc.

Inventor： Tae Ho Lee

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L29/41758 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/788 ,  H01L29/7887

Abstract: A nonvolatile memory device includes a plurality of twin cells arrayed on a substrate. Each of the plurality of twin cells includes a drain mesa protruding from a surface of a substrate. A first source and a second source are disposed in the substrate and spaced apart from the drain mesa. A first floating gate overlaps with a first sidewall surface of the drain mesa and extends onto the first source, and a second floating gate overlaps with a second sidewall surface of the drain mesa and extends onto the second source. Related methods are also provided.

Abstract translation: 非易失性存储器件包括排列在衬底上的多个双电池。 多个双孔单元中的每一个包括从基板的表面突出的排水台面。 第一源极和第二源极设置在衬底中并与漏极台面间隔开。 第一浮栅与漏极台面的第一侧壁表面重叠并且延伸到第一源极上，并且第二浮栅与漏极台面的第二侧壁表面重叠并且延伸到第二源极上。 还提供了相关方法。