公开(公告)号：US20150287463A1

公开(公告)日：2015-10-08

申请号：US14473313

申请日：2014-08-29

申请人： SK HYNIX INC.

发明人： Sung Lae OH ,  Dong Hyuk KIM

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C5/025 ,  G11C16/0483

摘要： A nonvolatile memory device includes a cell array, a distributed page buffer including a plurality of page buffer units disposed below the cell array, the plurality of page buffer units having a certain size; and a distributed page buffer control circuit including a plurality of page buffer control circuit units, each page buffer control circuit unit being arranged at one side of a corresponding page buffer unit, and configured to control operations of the corresponding page buffer unit, the plurality of page buffer control circuit units each having a predetermined size.

摘要翻译： 非易失性存储器件包括单元阵列，包括设置在单元阵列下方的多个页缓冲器单元的分布式页缓冲器，所述多个页缓冲单元具有一定大小; 以及包括多个页面缓冲器控制电路单元的分布式页面缓冲器控制电路，每个页面缓冲器控制电路单元布置在对应的页面缓冲单元的一侧，并且被配置为控制对应的页面缓冲器单元的操作， 每个具有预定尺寸的页面缓冲器控制电路单元。

公开(公告)号：US20210241835A1

公开(公告)日：2021-08-05

申请号：US16932522

申请日：2020-07-17

申请人： SK hynix Inc.

发明人： Sung Lae OH ,  Dong Hyuk KIM ,  Tae Sung PARK ,  Soo Nam JUNG

IPC分类号： G11C16/24

摘要： A semiconductor device including a page buffer is disclosed, which reduces the number of lines of the page buffer. The semiconductor device includes a plurality of bit lines, classified into a first group and a second group, that are arranged alternating, a first page buffer circuit coupled to the plurality of bit lines and a plurality of connection lines corresponding to the plurality of bit lines, and a second page buffer circuit coupled to the plurality of connection lines. Each of the first group and the second group includes a plurality of bit-line pairs classified into odd bit lines and even bit lines. The plurality of connection lines includes odd connection lines and even connection lines, and odd connection lines corresponding to the odd bit lines are arranged contiguous to each other, and even connection lines corresponding to the even bit lines are arranged contiguous to each other.

公开(公告)号：US20230230920A1

公开(公告)日：2023-07-20

申请号：US18192322

申请日：2023-03-29

申请人： SK hynix Inc.

发明人： Dong Hyuk KIM ,  Sung Lae OH ,  Tae Sung PARK ,  Soo Nam JUNG

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/535 ,  G11C7/18 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L23/535 ,  G11C7/18 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

摘要： A semiconductor device includes a first connection pattern; a bit line disposed over the first connection pattern in a vertical direction; and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern, and formed as an island when viewed along the vertical direction. A predetermined number of the bit-line contact pads are spaced apart from each other by a predetermined distance in a first direction, when viewed along the vertical direction.

公开(公告)号：US20210066313A1

公开(公告)日：2021-03-04

申请号：US16810813

申请日：2020-03-05

申请人： Sk hynix Inc.

发明人： Tae Sung PARK ,  Sung Lae OH ,  Dong Hyuk KIM ,  Soo Nam JUNG

IPC分类号： H01L27/11 ,  H01L27/11582 ,  H01L27/112 ,  H01L27/108 ,  H01L27/11543 ,  H01L27/11551

摘要： A semiconductor memory device includes a stack disposed over a first substrate; an etch barrier including a plurality of dummy channels which pass through the stack and surround a coupling region; and a plurality of channels passing through the stack in a cell region outside the coupling region. The stack has a structure in which first dielectric layers and second dielectric layers are alternately stacked, inside the coupling region, and has a structure in which the first dielectric layers and electrode layers are alternately stacked, outside the coupling region.

公开(公告)号：US20210217479A1

公开(公告)日：2021-07-15

申请号：US16885192

申请日：2020-05-27

申请人： SK hynix Inc.

发明人： Sung Lae OH ,  Dong Hyuk KIM ,  Tae Sung PARK ,  Soo Nam JUNG

IPC分类号： G11C16/24 ,  G11C16/04 ,  G11C16/26

摘要： A semiconductor memory device includes a plurality of page buffers defined in active regions of a substrate; and a plurality of wiring lines disposed over the page buffers, and coupled to the page buffers through contacts. The plurality of wiring lines may include contact portions which are coupled with the contacts, respectively. The plurality of wiring lines may be configured into a bent shape such that the contact portions are offset toward center lines of the active regions.

公开(公告)号：US20210143173A1

公开(公告)日：2021-05-13

申请号：US17121940

申请日：2020-12-15

申请人： SK hynix Inc.

发明人： Sung Lae OH ,  Dong Hyuk KIM ,  Tae Sung PARK ,  Soo Nam JUNG

IPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11526 ,  H01L21/768 ,  H01L21/311 ,  H01L25/00 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11573

摘要： A method for manufacturing a semiconductor memory device may include: forming a pre-stack by alternately stacking a plurality of first dielectric layers and a plurality of second dielectric layers over a substrate which has a cell area and a connection area; forming a plurality of slits which pass through the pre-stack, such that a distance between the slits in the connection area is larger than a distance between the slits in the cell area; removing the second dielectric layers in the cell area and in a periphery of the connection area adjacent to the slits while leaving the second dielectric layer in a center of the connection area by injecting an etching solution for removing the second dielectric layers, through the slits; and forming electrode layers in spaces from which the second dielectric layers are removed.

公开(公告)号：US20230401157A1

公开(公告)日：2023-12-14

申请号：US18053003

申请日：2022-11-07

申请人： SK hynix Inc.

发明人： Dong Hyuk KIM ,  Tae Sung PARK ,  Sang Hyun SUNG ,  Sung Lae OH ,  Soo Nam JUNG

IPC分类号： G06F12/0895 ,  G06F12/0882 ,  G06F12/123

CPC分类号： G06F12/0895 ,  G06F12/0882 ,  G06F12/125

摘要： A unit page buffer block includes first to fourth page buffer pairs. Each of the page buffer pairs includes a common column decoder block; and an upper page buffer stage and a lower page buffer stage electrically and commonly connected to the common column decoder block. Each of the upper page buffer stages includes an upper selection block; an upper latch block; and an upper cache block. Each of the lower page buffer stage includes a lower selection block; a lower latch block; and a lower cache block. Each of the upper selection blocks includes first to fourth sub-selection blocks. Each of the upper and lower latch blocks includes first to twelfth upper sub-latch blocks. Each of the upper and lower cache blocks includes first to twelfth upper sub-cache blocks. Each of the common column decoder block includes first to third sub-common column decoder blocks arranged in a row direction.

公开(公告)号：US20210287982A1

公开(公告)日：2021-09-16

申请号：US17079267

申请日：2020-10-23

申请人： SK hynix Inc.

发明人： Dong Hyuk KIM ,  Sung Lae OH ,  Tae Sung PARK ,  Soo Nam JUNG

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/535 ,  H01L27/11551 ,  H01L27/11529 ,  H01L27/11578 ,  H01L27/11573

摘要： A semiconductor device is disclosed, which relates to a three-dimensional (3D) semiconductor memory device. The semiconductor device includes a first connection pattern, a bit line disposed over the first connection pattern in a vertical direction, and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern so that the bit-line contact pad, and formed as an island when viewed along the vertical direction.

公开(公告)号：US20210074367A1

公开(公告)日：2021-03-11

申请号：US16810774

申请日：2020-03-05

申请人： SK hynix Inc.

发明人： Sung Lae OH ,  Dong Hyuk KIM ,  Tae Sung PARK ,  Soo Nam JUNG

IPC分类号： G11C16/26 ,  G11C16/04 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G06F12/0895

摘要： A semiconductor memory device includes a memory cell array; a page buffer circuit including a plurality of page buffers which are coupled to the memory cell array through a plurality of bit lines which extend in a second direction intersecting with a first direction; and a cache latch circuit including a plurality of cache latches which are coupled to the plurality of page buffers. The plurality of cache latches have a two-dimensional arrangement in the first direction and the second direction. Among the plurality of cache latches, an even cache latch and an odd cache latch which share a data line and an inverted data line are disposed adjacent to each other in the first direction.

公开(公告)号：US20210057360A1

公开(公告)日：2021-02-25

申请号：US16811481

申请日：2020-03-06

申请人： SK hynix Inc.

发明人： Sung Lae OH ,  Dong Hyuk KIM ,  Tae Sung PARK

IPC分类号： H01L23/00 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  G06F3/06

摘要： A semiconductor memory device includes: a plurality of page buffers disposed on a substrate; and a plurality of pads exposed to one surface of a dielectric layer covering the page buffers, and coupled to the respective page buffers. The substrate comprises a plurality of high voltage regions and a plurality of low voltage regions which are alternately disposed in a second direction crossing a first direction. Each of the plurality of page buffers comprises a sensing unit and a bit line select transistor coupled between the sensing unit and the one of the plurality of pads. The bit line select transistors of the plurality of page buffers are disposed in the plurality of high voltage regions, and the plurality of pads are distributed and disposed in a plurality of pad regions which correspond to the high voltage regions and are spaced apart from each other in the second direction.