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    SEMICONDUCTOR MEMORY DEVICE INCLUDING UNIT PAGE BUFFER BLOCKS HAVING FOUR PAGE BUFFER PAIRS
    1.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE INCLUDING UNIT PAGE BUFFER BLOCKS HAVING FOUR PAGE BUFFER PAIRS 审中-公开

    公开(公告)号：US20230401157A1

    公开(公告)日：2023-12-14

    申请号：US18053003

    申请日：2022-11-07

    申请人： SK hynix Inc.

    发明人： Dong Hyuk KIM ,  Tae Sung PARK ,  Sang Hyun SUNG ,  Sung Lae OH ,  Soo Nam JUNG

    IPC分类号： G06F12/0895 ,  G06F12/0882 ,  G06F12/123

    CPC分类号： G06F12/0895 ,  G06F12/0882 ,  G06F12/125

    摘要： A unit page buffer block includes first to fourth page buffer pairs. Each of the page buffer pairs includes a common column decoder block; and an upper page buffer stage and a lower page buffer stage electrically and commonly connected to the common column decoder block. Each of the upper page buffer stages includes an upper selection block; an upper latch block; and an upper cache block. Each of the lower page buffer stage includes a lower selection block; a lower latch block; and a lower cache block. Each of the upper selection blocks includes first to fourth sub-selection blocks. Each of the upper and lower latch blocks includes first to twelfth upper sub-latch blocks. Each of the upper and lower cache blocks includes first to twelfth upper sub-cache blocks. Each of the common column decoder block includes first to third sub-common column decoder blocks arranged in a row direction.

    MEMORY DEVICE INCLUDING ROW DECODER
    2.
    发明公开
    MEMORY DEVICE INCLUDING ROW DECODER 审中-公开

    公开(公告)号：US20230207013A1

    公开(公告)日：2023-06-29

    申请号：US17725372

    申请日：2022-04-20

    申请人： SK hynix Inc.

    发明人： Sang Hyun SUNG ,  Sung Lae OH

    IPC分类号： G11C16/08 ,  G11C16/24

    CPC分类号： G11C16/08 ,  G11C16/24

    摘要： A memory device includes a memory cell array included in a first semiconductor layer, and including a plurality of row lines that extend in a first direction, each of the plurality of row lines having a pad part disposed in a slimming region; a row decoder included in a second semiconductor layer disposed under the first semiconductor layer, and overlapping the memory cell array in a vertical direction; slimming regions disposed on both sides of the row decoder in the first direction; and a plurality of wiring lines coupling the pad parts of the plurality of row lines and the row decoder.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210210475A1

    公开(公告)日：2021-07-08

    申请号：US16890653

    申请日：2020-06-02

    申请人： SK hynix Inc.

    发明人： Sang Hyun SUNG ,  Young Ki KIM ,  Jin Ho KIM ,  Byung Hyun JUN

    IPC分类号： H01L25/18 ,  H01L27/11582 ,  H01L23/00 ,  H01L23/528 ,  H01L27/11573

    摘要： A semiconductor memory device includes: a first pad layer in a surface of a memory chip including a cell region in which a memory cell array coupled to a plurality of row lines and a step region including staggered step portions of the plurality of row lines, and including a plurality of first pads that are coupled to the step portions; a second pad layer in a surface of a circuit chip bonded to the surface of the memory chip, and having a plurality of second pads coupled to a plurality of pass transistors defined in the circuit chip; a first redistribution line disposed in the first pad layer that couples one of the step portions and one of the pass transistors; and a second redistribution line disposed in the second pad layer that couples another one of the step portions and another one of the pass transistors.

    MEMORY DEVICE HAVING VERTICAL STRUCTURE
    6.
    发明申请
    MEMORY DEVICE HAVING VERTICAL STRUCTURE 有权

    公开(公告)号：US20220293619A1

    公开(公告)日：2022-09-15

    申请号：US17828417

    申请日：2022-05-31

    申请人： SK hynix Inc.

    发明人： Jin Ho KIM ,  Kwang Hwi PARK ,  Sang Hyun SUNG ,  Sung Lae OH ,  Chang Woon CHOI

    IPC分类号： H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11526

    摘要： A memory device includes a cell wafer including a memory cell array; and a peripheral wafer including a row control circuit, a column control circuit and a peripheral circuit which control the memory cell array, and stacked on and bonded to the cell wafer in a first direction. The peripheral wafer includes a first substrate having a first surface and a second surface which face away from each other in the first direction; a first logic structure disposed on the first surface of the first substrate, and including the row control circuit and the column control circuit; and a second logic structure disposed on the second surface of the first substrate, and including the peripheral circuit.

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220139449A1

    公开(公告)日：2022-05-05

    申请号：US17171632

    申请日：2021-02-09

    申请人： SK hynix Inc.

    发明人： Sang Hyun SUNG ,  Sung Lae OH ,  Je Hyun CHOI

    IPC分类号： G11C11/417 ,  G11C11/412 ,  H01L23/00 ,  H01L27/11

    摘要： A semiconductor device includes a first wafer including a row decoder region in which a plurality of pass transistors are arranged in a row direction and a column direction; a plurality of first bonding pads, respectively coupled to the plurality of pass transistors that are disposed in a plurality of rows on one surface of the first wafer in the row decoder region; and a plurality of second bonding pads disposed on the one surface of the first wafer in the row decoder region, wherein the plurality of second bonding pads are disposed in a different row from the plurality of first bonding pads and are offset in the row direction with respect to the plurality of first bonding pads.

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210272631A1

    公开(公告)日：2021-09-02

    申请号：US17030266

    申请日：2020-09-23

    申请人： SK hynix Inc.

    发明人： Jin Ho KIM ,  Sang Hyun SUNG ,  Sung Lae OH

    IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  H01L27/115 ,  G11C16/26 ,  G11C16/10

    摘要： A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first substrate layer including a logic circuit, and a plurality of second substrate layers stacked on the first substrate layer, the plurality of second substrate layers including a memory cell array. Each of the plurality of second substrate layers includes, a transfer circuit, coupled to a row line of the memory cell array, that is disposed over the second substrate layer and selectively coupled to a global row line.

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
    10.
    发明公开
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230282603A1

    公开(公告)日：2023-09-07

    申请号：US17855241

    申请日：2022-06-30

    申请人： SK hynix Inc.

    发明人： Sung Lae OH ,  Sang Hyun SUNG ,  Hyun Soo SHIN ,  Kang Sik CHOI

    IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18

    CPC分类号： H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/1434

    摘要： A three-dimensional semiconductor device includes a peripheral circuit device layer that includes a page buffer area, a pass transistor area adjacent to the page buffer layer, and a logic transistor area adjacent to the pass transistor area in the first direction, and a memory cell device layer that includes a cell area and a staircase area extending from the cell area. The peripheral circuit device layer includes transistors, peripheral circuit via plugs, and peripheral circuit interconnection layers on a substrate. The memory cell device layer includes word line stack including interlayer insulating layers and word lines alternately stacked, the word line stack including end portions stacked in a staircase in the staircase area; a bit line array including bit lines arranged in the cell area; and word line pillars electrically connected to the end portions of the word lines in the staircase area, respectively.