公开(公告)号：US12068019B2

公开(公告)日：2024-08-20

申请号：US18322409

申请日：2023-05-23

申请人： SK hynix Inc.

发明人： Chan Hui Jeong

IPC分类号： G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4099

CPC分类号： G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4099

摘要： An internal voltage generation circuit includes an enable control circuit configured to generate a final enable signal by limiting an activation time point of an enable signal to a point in time after a reset time, after the enable signal is inactivated. The internal voltage generation circuit also includes a start-up control circuit configured to perform a reset operation during the reset time and generate a start-up signal based on the final enable signal, a reference voltage generation circuit configured to generate a reference voltage based on the start-up signal, a current generation circuit configured to generate a reference current based on the reference voltage, and a voltage generation circuit configured to generate an internal voltage based on the reference current.

公开(公告)号：US10599170B2

公开(公告)日：2020-03-24

申请号：US16237379

申请日：2018-12-31

申请人： SK hynix Inc.

发明人： Chan Hui Jeong

IPC分类号： G05F1/10 ,  G11C5/14 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C11/00 ,  G05F3/02

摘要： Provided herein may be an internal voltage generation circuit and a memory device having the same. The internal voltage generation circuit may include an integration circuit configured to generate an initial voltage that increases with a constant slope based on an input voltage, a selection circuit configured to compare a feedback voltage with a reference voltage and then output the initial voltage or the reference voltage as an output voltage, and a first internal voltage generation circuit configured to generate an internal voltage by being supplied with an external supply voltage or by being blocked from being supplied with the external supply voltage based on a result of a comparison between the output voltage and the feedback voltage and to generate the feedback voltage by dividing the internal voltage.

公开(公告)号：US11551744B2

公开(公告)日：2023-01-10

申请号：US17158767

申请日：2021-01-26

申请人： SK hynix Inc.

发明人： Chan Hui Jeong

IPC分类号： G11C11/4093 ,  G11C11/4099 ,  G11C5/06 ,  G11C11/4091 ,  G11C11/4094

摘要： A memory device according to the present technology includes a memory cell array configured to include planes having a plurality of memory cells, a page buffer connected to at least one memory cell among the memory cells through a bit line and configured to perform a sensing operation of reading data stored in the at least one memory cell connected to the bit line, a common reference voltage generator configured to generate a common reference voltage, a plurality of merged buffers configured to generate a reference signal using the common reference voltage, and control logic configured to control an operation of the common reference voltage generator and the merged buffers so that page buffer control signals generated based on the reference signal are supplied to the page buffer.

公开(公告)号：US11264097B2

公开(公告)日：2022-03-01

申请号：US16906784

申请日：2020-06-19

申请人： SK hynix Inc.

发明人： Chan Hui Jeong

IPC分类号： G11C5/14 ,  G11C15/04 ,  G05F3/26

摘要： A voltage generation circuit includes a driver configured to generate an internal voltage by driving an external voltage depending on a driving signal; an amplifier configured to generate the driving signal depending on a result of comparing a reference voltage and a feedback voltage; and a switch configured to delay a decrease of the internal voltage by precharging a node of the amplifier with a predetermined voltage depending on a control signal.

公开(公告)号：US11656131B2

公开(公告)日：2023-05-23

申请号：US17353099

申请日：2021-06-21

申请人： SK hynix Inc.

发明人： Chan Hui Jeong ,  Suk Hwan Choi

IPC分类号： G01K7/00 ,  H03F3/45 ,  H03M1/12

CPC分类号： G01K7/00 ,  H03F3/45179 ,  H03F3/45475 ,  H03M1/12 ,  H03F2200/129 ,  H03F2203/45116

摘要： The digital temperature sensing circuit includes a temperature voltage generator configured to generate a temperature voltage varying with a temperature in response to a first reference voltage, divide a supply voltage in response to a second reference voltage, and generate a high voltage and a low voltage, a code voltage generator configured to divide the second reference voltage based on the high voltage and the low voltage and output divided voltages having different voltage levels, and a mode selector supplied with the temperature voltage and the divided voltages, and configured to output a first code or a second code in response to a mode select signal, wherein the first code and the second code have different numbers of bits.

公开(公告)号：US11451223B2

公开(公告)日：2022-09-20

申请号：US17167553

申请日：2021-02-04

申请人： SK hynix Inc.

发明人： Chan Hui Jeong

IPC分类号： G11C7/10 ,  H03K17/10 ,  G06F3/06 ,  G11C7/22

摘要： The present technology relates to an electronic device. A driver for generating a signal that satisfies a characteristic required according to a type of a signal includes a current controller configured to control total current flowing through the driver based on a selected signal, among a plurality of signals, applied to a page buffer that stores data, a load controller configured to control a magnitude of a load of an output terminal of the driver based on the selected signal and a cap compensator configured to control the magnitude of the load of the output terminal by increasing or decreasing a capacitance of the load of the output terminal based on the selected signal.

公开(公告)号：US12125536B2

公开(公告)日：2024-10-22

申请号：US17703625

申请日：2022-03-24

申请人： SK hynix Inc.

发明人： Chan Hui Jeong ,  Dong Hun Kwak ,  Se Chun Park

IPC分类号： G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3459 ,  G11C16/0483

摘要： The present disclosure relates to an electronic device. A memory device includes a plurality of memory cells coupled to a plurality of word lines, a voltage generator generating program-related voltages to be applied to the plurality of word lines, an address decoder transferring the program-related voltages to the plurality of word lines, and an operation controller controlling the voltage generator and the address decoder to apply a program voltage to a selected word line among the plurality of word lines, a second pass voltage to adjacent word lines neighboring the selected word line, a first pass voltage to remaining word lines except for the selected word line and the adjacent word lines, and to apply a ground voltage to the selected word line and the first pass voltage to the adjacent word lines during a first period.

公开(公告)号：US11783889B2

公开(公告)日：2023-10-10

申请号：US18078732

申请日：2022-12-09

申请人： SK hynix Inc.

发明人： Chan Hui Jeong

IPC分类号： G11C11/4093 ,  G11C11/4099 ,  G11C5/06 ,  G11C11/4091 ,  G11C11/4094

CPC分类号： G11C11/4093 ,  G11C5/06 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099

摘要： A memory device according to the present technology includes a memory cell array configured to include planes having a plurality of memory cells, a page buffer connected to at least one memory cell among the memory cells through a bit line and configured to perform a sensing operation of reading data stored in the at least one memory cell connected to the bit line, a common reference voltage generator configured to generate a common reference voltage, a plurality of merged buffers configured to generate a reference signal using the common reference voltage, and control logic configured to control an operation of the common reference voltage generator and the merged buffers so that page buffer control signals generated based on the reference signal are supplied to the page buffer.

公开(公告)号：US11694741B2

公开(公告)日：2023-07-04

申请号：US17411699

申请日：2021-08-25

申请人： SK hynix Inc.

发明人： Chan Hui Jeong

IPC分类号： G11C11/4072 ,  G11C11/4099 ,  G11C11/4076 ,  G11C11/4074

CPC分类号： G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4099

摘要： An internal voltage generation circuit includes an enable control circuit configured to generate a final enable signal by limiting an activation time point of an enable signal to a point in time after a reset time, after the enable signal is inactivated. The internal voltage generation circuit also includes a start-up control circuit configured to perform a reset operation during the reset time and generate a start-up signal based on the final enable signal, a reference voltage generation circuit configured to generate a reference voltage based on the start-up signal, a current generation circuit configured to generate a reference current based on the reference voltage, and a voltage generation circuit configured to generate an internal voltage based on the reference current.

公开(公告)号：US11099080B2

公开(公告)日：2021-08-24

申请号：US16030071

申请日：2018-07-09

申请人： SK hynix Inc.

发明人： Chan Hui Jeong ,  Suk Hwan Choi

IPC分类号： G01K7/00 ,  H03F3/45 ,  H03M1/12

摘要： The digital temperature sensing circuit includes a temperature voltage generator configured to generate a temperature voltage varying with a temperature in response to a first reference voltage, divide a supply voltage in response to a second reference voltage, and generate a high voltage and a low voltage, a code voltage generator configured to divide the second reference voltage based on the high voltage and the low voltage and output divided voltages having different voltage levels, and a mode selector supplied with the temperature voltage and the divided voltages, and configured to output a first code or a second code in response to a mode select signal, wherein the first code and the second code have different numbers of bits.