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公开(公告)号：US20180217785A1
公开(公告)日：2018-08-02
申请号：US15644193
申请日：2017-07-07
Applicant: SK hynix Inc.
Inventor： Dong Jae SHIN
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0611 , G06F3/0679 , G06F3/0688
Abstract: A data storage device includes a nonvolatile memory device; and a controller suitable for controlling the nonvolatile memory device through a command, the controller comprising a memory controller including a queue which includes multiple slots, each of the multiple slots being mapped to one type among a plurality of types of the command, and suitable for processing a descriptor for the command enqueued to the queue to generate the command; and a processor suitable for requesting one slot of the multiple slots mapped to one type among the plurality of types of the command, to the memory controller, and enqueuing, when allocated with the one slot, the descriptor for the command, to the one slot.
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公开(公告)号：US20150113207A1
公开(公告)日：2015-04-23
申请号：US14155016
申请日：2014-01-14
Applicant: SK hynix Inc.
Inventor： Dong Jae SHIN
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F2212/7201
Abstract: A method for operating a data storage device includes grouping memory blocks of a nonvolatile memory device based on program counts or erase counts of the respective memory blocks, into a first group and a second group, which has program counts or erase counts larger than the first group, performing a reprogram operation for memory blocks included in the first group, and performing a read retry operation for a selected memory cell of a memory block included in the first group or the second group, based on a read retry voltage set for each of the first group and the second group, when an error of data read from the selected memory cell is not correctable.
Abstract translation: 一种用于操作数据存储设备的方法包括：基于各个存储器块的程序计数或擦除计数将非易失性存储器件的存储块分组成具有比第一组和第二组的程序计数或擦除计数大的第一组和第二组 组，对包括在第一组中的存储块执行重新编程操作，并且基于为每个的设置的读取重试电压为包括在第一组或第二组中的存储器块的选定存储单元执行读取重试操作 当从所选择的存储单元读取数据的错误是不可校正的时候，第一组和第二组。
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公开(公告)号：US20210181985A1
公开(公告)日：2021-06-17
申请号：US16893055
申请日：2020-06-04
Applicant: SK hynix Inc.
Inventor： Dong Jae SHIN
IPC: G06F3/06 , G11C11/408
Abstract: Provided herein may be a storage device configured to check a status of a memory device based on data read without output of a status check command, and determine a subsequent command to be generated. The storage device may include a memory device and a memory controller configured to control the memory device. The memory device may include a read data generator configured to generate new read data including both read data corresponding to a read command received from the memory controller and information indicating a status of the memory device. The memory controller may include: a status information determiner configured to determine the status of the memory device based on the new read data received from the read data generator and generate status information and a command generator configured to generate a command to be output to the memory device based on the status information.
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4.发明申请STORAGE DEVICE INCLUDING MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME 有权存储器件，包括存储器控制器和包括其的存储器系统公开(公告)号：US20160313928A1
公开(公告)日：2016-10-27
申请号：US14877631
申请日：2015-10-07
Applicant: SK hynix Inc.
Inventor： Dong Yeob CHUN , Dong Jae SHIN
IPC: G06F3/06
CPC classification number: G06F3/0616 , G06F3/0659 , G06F3/0679
Abstract: Disclosed is a storage device, including: a memory controller configured to generate mode maintenance information or mode change information in response to a command received from a host; and a memory device configured to perform a selected operation in a previous mode when the mode maintenance information is received, and change a mode and perform the selected operation when the mode change information is received.
Abstract translation: 公开了一种存储装置，包括：存储器控制器，被配置为响应于从主机接收的命令生成模式维护信息或模式改变信息; 以及存储装置，被配置为当接收到模式维护信息时在先前模式中执行选择的操作，并且当接收到模式改变信息时，改变模式并执行所选择的操作。
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公开(公告)号：US20150113305A1
公开(公告)日：2015-04-23
申请号：US14143889
申请日：2013-12-30
Applicant: SK hynix Inc.
Inventor： Dong Jae SHIN , Soo Nyun KIM
IPC: G06F1/32
CPC classification number: G06F3/0634 , G06F1/3237 , G06F1/3275 , G06F1/3287 , G06F1/3293 , G06F3/0604 , G06F3/0625 , G06F3/0679 , Y02D10/122 , Y02D10/14 , Y02D10/171
Abstract: A data storage device includes a nonvolatile memory device; and a controller suitable for controlling an operation of the nonvolatile memory device based on a request from a host device, wherein the controller includes a first core activated in a normal mode and a second core activated in a standby mode.
Abstract translation: 数据存储装置包括非易失性存储装置; 以及适于基于来自主机设备的请求来控制所述非易失性存储器件的操作的控制器，其中，所述控制器包括以正常模式激活的第一内核和在待机模式下激活的第二核。
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Patent Agency Ranking
公开(公告)号：US20240393965A1
公开(公告)日：2024-11-28
申请号：US18478429
申请日：2023-09-29
Applicant: SK hynix Inc.
Inventor： Young Gyun KIM , Hyeon Uk LEE , Dong Jae SHIN
Abstract: A storage device may include a memory and a controller. The memory may include a plurality of memory units. The controller may transmit a read command for a target memory unit among the plurality of memory units to the memory, read a state value from the memory after transmitting the read command to the memory, and determine that all bits of data stored in the target memory unit are 1 when the state value is a first value, and determine that all bits of the data stored in the target memory unit are 0 when the state value is a second value.
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公开(公告)号：US20150178009A1
公开(公告)日：2015-06-25
申请号：US14198248
申请日：2014-03-05
Applicant: SK hynix Inc.
Inventor： Dong Jae SHIN , Seung Jin PARK
CPC classification number: G06F1/3275 , G06F1/3268 , G06F12/0246 , Y02D10/154 , Y02D50/20
Abstract: A data processing system includes a host device including a first volatile memory device, and a data storage device including a second volatile memory device and a nonvolatile memory device, and suitable for storing data to be accessed by the host device. The data storage device uploads data stored in the second volatile memory device to the first volatile memory device before the data storage device in a normal mode enters a power-save mode.
Abstract translation: 数据处理系统包括主机设备，其包括第一易失性存储器设备和包括第二易失性存储器设备和非易失性存储器设备的数据存储设备，并且适于存储要由主机设备访问的数据。 在正常模式下的数据存储装置进入省电模式之前，数据存储装置将存储在第二易失性存储装置中的数据上载到第一易失性存储装置。
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公开(公告)号：US20150149740A1
公开(公告)日：2015-05-28
申请号：US14161413
申请日：2014-01-22
Applicant: SK hynix Inc.
Inventor： Dong Jae SHIN , Soo Nyun KIM
CPC classification number: G06F12/023 , G06F12/0246 , G06F21/79 , G06F2212/1052 , G06F2212/7211 , Y02D10/13
Abstract: A data processing system includes a data storage device including memory cells, which are erased to an erasure state and programmed to program states to store data, and a host device suitable for accessing the data, wherein the data storage device programs a first memory cell to a first state other than the erasure state to delete data of the first memory cell in response to a request of the host device.
Abstract translation: 数据处理系统包括：数据存储装置，包括被擦除为擦除状态并被编程为编程状态以存储数据的存储器单元;以及适于访问数据的主机，其中数据存储装置将第一存储器单元编程为 除了所述擦除状态以响应于所述主机设备的请求来删除所述第一存储器单元的数据的第一状态。
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公开(公告)号：US20250022525A1
公开(公告)日：2025-01-16
申请号：US18510664
申请日：2023-11-16
Applicant: SK hynix Inc.
Inventor： Young Gyun KIM , Hye Lyoung LEE , Seung Gu JI , Dong Jae SHIN
Abstract: A storage device includes a memory device and a controller. The memory device includes a plurality of memory regions. The controller is configured to perform a test operation on a target memory region among the memory regions when it is impossible to determine a second program standby time amount by which a second program operation remains as not performed on the target memory region after a first program operation is performed on the target memory region, and configured to control, according to a result of the test operation, the memory device to perform an adjusted second program operation on the target memory region.
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公开(公告)号：US20190138455A1
公开(公告)日：2019-05-09
申请号：US16028570
申请日：2018-07-06
Applicant: SK hynix Inc.
Inventor： Dong Jae SHIN
IPC: G06F12/1009 , G06F3/06
Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller controls a semiconductor memory device including a plurality of pages. The memory controller may include a processing unit and a command control unit. The processing unit receives a command and a logical address corresponding to the command from a host, and generates a command physical address by converting the logical address. The command control unit temporarily stores a cache physical address corresponding to cache data that is cached in a page buffer of the semiconductor memory device and converts the command by comparing the cache physical address to the command physical address.
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