公开(公告)号：US11563030B2

公开(公告)日：2023-01-24

申请号：US17342981

申请日：2021-06-09

申请人： SK hynix Inc.

发明人： Sung-Lae Oh ,  Dong-Hyuk Kim ,  Tae-Sung Park ,  Soo-Nam Jung ,  Chang-Woon Choi

IPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/02 ,  H01L23/528

摘要： A semiconductor memory device includes a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; stepped grooves provided in the stacked structure, the stepped grooves having different depths from each other; and an opening portion penetrating the stacked structure to contact the substrate and having steps on sidewalls, the steps having heights corresponding to depth differences between stepped grooves.

公开(公告)号：US10971487B2

公开(公告)日：2021-04-06

申请号：US16829918

申请日：2020-03-25

申请人： SK hynix Inc.

发明人： Sung-Lae Oh ,  Dong-Hyuk Kim ,  Soo-Nam Jung

IPC分类号： G11C8/00 ,  H01L25/18 ,  H01L27/11556 ,  H01L27/11526 ,  H01L23/00 ,  G11C16/08 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11573

摘要： A semiconductor memory device includes a cell wafer including a first plane and a second plane which are disposed to be adjacent to each other in a first direction and each include a plurality of memory cells; and a peripheral wafer including a row decoder which simultaneously controls the first and second planes and first and second page buffer circuits which control the first and second planes, respectively. The cell wafer includes, on one surface thereof bonded to the peripheral wafer, a first pad which is coupled in common with the first plane and the second plane, and the peripheral wafer includes, on one surface thereof bonded to the cell wafer, a second pad which is coupled with the row decoder and is bonded to the first pad.

公开(公告)号：US10664395B2

公开(公告)日：2020-05-26

申请号：US16198413

申请日：2018-11-21

申请人： SK hynix Inc.

发明人： Sung-Lae Oh ,  Dong-Hyuk Kim ,  Soo-Nam Jung

IPC分类号： G11C16/04 ,  G06F12/0806

摘要： A memory device includes a plurality of bit lines; a page buffer circuit including a plurality of page buffers which are electrically coupled to the plurality of bit lines; and a cache circuit including a plurality of caches which are electrically coupled to the plurality of page buffers, wherein a number of stages of the page buffer circuit is less than a number of stages of the cache circuit.

公开(公告)号：US10141326B1

公开(公告)日：2018-11-27

申请号：US15885328

申请日：2018-01-31

申请人： SK hynix Inc.

发明人： Sung-Lae Oh ,  Dong-Hyuk Kim ,  Sang-Hyun Sung ,  Seong-Hun Jung ,  Soo-Nam Jung

IPC分类号： H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/1157 ,  G11C16/08 ,  G11C16/24

摘要： A semiconductor memory device includes a peripheral circuit element provided over a lower substrate; an upper substrate provided over an interlayer dielectric layer which partially covers the peripheral circuit element; a memory cell array including a channel structure which extends in a first direction perpendicular to a top surface of the upper substrate and a plurality of gate lines which are stacked over the upper substrate to surround the channel structure; and a plurality of transistors electrically coupling the gate lines to the peripheral circuit element. The transistors include a gate electrode provided over the interlayer dielectric layer and disposed to overlap with the memory cell array in the first direction; a plurality of vertical channels passing through the gate electrode in the first direction and electrically coupled to the gate lines, respectively; and gate dielectric layers disposed between the vertical channels and the gate electrode.

公开(公告)号：US10020062B1

公开(公告)日：2018-07-10

申请号：US15792983

申请日：2017-10-25

申请人： SK hynix Inc.

发明人： Sung-Lae Oh ,  Jin-Ho Kim ,  Dong-Hyuk Kim ,  Soo-Nam Jung

IPC分类号： G11C16/16 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11514 ,  G11C16/34

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3477 ,  H01L27/11514 ,  H01L27/1157 ,  H01L27/11582

摘要： A nonvolatile memory device includes well regions formed in a substrate and arranged in a first direction; a memory block including sub blocks which are formed over the substrate and correspond to the well regions, respectively; and bit lines disposed over the memory block, and extending in the first direction. Each of the sub blocks includes channel layers which are formed in a vertical direction between a corresponding well region and the bit lines, word lines and at least one drain select line and at least one erase prevention line, which are stacked over the substrate along the channel layers. In an erase operation, an erase voltage is applied to a well region corresponding to a selected sub block and an erase preventing voltage is applied to an erase prevention line included in an unselected sub block, the erase voltage may be prevented from being transferred to the unselected sub block.

公开(公告)号：US11211328B2

公开(公告)日：2021-12-28

申请号：US16747171

申请日：2020-01-20

申请人： SK hynix Inc.

发明人： Sung-Lae Oh ,  Dong-Hyuk Kim ,  Soo-Nam Jung

IPC分类号： H01L27/11578 ,  H01L23/528 ,  G11C7/18 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11529

摘要： A semiconductor memory device includes a memory chip defined with a first pad on one surface thereof; and a circuit chip defined with a second pad which is coupled with the first pad, on one surface thereof bonded with the one surface of the memory chip. The memory chip comprising: a memory cell array; a bit line disposed in a first wiring layer between the one surface and the memory cell array, and separated into a first bit line section and a second bit line section; and a power pad disposed in a space between the first bit line section and the second bit line section in the first wiring layer, and coupled with the first pad.

公开(公告)号：US10680004B2

公开(公告)日：2020-06-09

申请号：US16041149

申请日：2018-07-20

申请人： SK hynix Inc.

发明人： Sung-Lae Oh ,  Dong-Hyuk Kim ,  Soo-Nam Jung

IPC分类号： H01L27/11551 ,  G11C5/06 ,  H01L27/11578 ,  G11C16/00 ,  G11C7/18 ,  G11C8/14

摘要： A semiconductor memory device comprises a memory cell array disposed on a substrate, a plurality of bit lines disposed on the a memory cell array, each bit line extending in a first direction parallel to the top surface of the substrate and divided into a first bit line section and a second bit line section, and a plurality of source line pads disposed at the same layer as the bit lines between the first bit line sections of the bit lines and the second bit line sections of the bit lines.

公开(公告)号：US10062765B2

公开(公告)日：2018-08-28

申请号：US15651058

申请日：2017-07-17

申请人： SK hynix Inc.

发明人： Sung-Lae Oh ,  Dong-Hyuk Kim ,  Soo-Nam Jung ,  Je-Hyun Choi

IPC分类号： G11C8/00 ,  H01L29/51 ,  H01L27/115 ,  G11C5/02 ,  G11C16/04 ,  H01L27/12

CPC分类号： H01L29/517 ,  G11C5/025 ,  G11C7/18 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/12 ,  H01L29/513 ,  H01L29/518

摘要： A nonvolatile memory device includes bit lines arranged in a first direction over a substrate; a memory cell array disposed between the substrate and the bit lines, and including a plurality of planes which are arranged in a second direction perpendicular to the first direction; page buffer circuits disposed between the substrate and the memory cell array; contact pads disposed between the substrate and the memory cell array, the contact pads being suitable for electrically coupling the bit lines and the page buffer circuits; and routing lines disposed at the same layer as the contact pads, and extending in the second direction, wherein the contact pads are disposed to overlap with at least two lines which are arranged in the second direction, and the routing lines are formed in a bent pattern to pass between the contact pads which are disposed to overlap with different lines.

公开(公告)号：US11063061B2

公开(公告)日：2021-07-13

申请号：US16515922

申请日：2019-07-18

申请人： SK hynix Inc.

发明人： Sung-Lae Oh ,  Dong-Hyuk Kim ,  Tae-Sung Park ,  Soo-Nam Jung ,  Chang-Woon Choi

IPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/02 ,  H01L23/528

摘要： A semiconductor memory device includes a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; stepped grooves provided in the stacked structure, the stepped grooves having different depths from each other; and an opening portion penetrating the stacked structure to contact the substrate and having steps on sidewalls, the steps having heights corresponding to depth differences between stepped grooves.

公开(公告)号：US10789172B2

公开(公告)日：2020-09-29

申请号：US16209174

申请日：2018-12-04

申请人： SK hynix Inc.

发明人： Sung-Lae Oh ,  Dong-Hyuk Kim ,  Soo-Nam Jung

IPC分类号： G11C16/10 ,  G06F12/0882 ,  G06F12/02 ,  G11C16/08 ,  G11C16/26 ,  G11C7/10 ,  G11C16/24

摘要： A memory device includes a plurality of bit lines extending in a first direction and arranged in a second direction perpendicular to the first direction; a page buffer circuit including a plurality of page buffers which are electrically coupled to the plurality of bit lines; and a cache circuit including a plurality of caches which are electrically coupled to the plurality of page buffers, wherein the page buffer circuit is divided into a plurality of page buffer regions and is laid out at both sides of the cache circuit in the first direction.