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    METHOD OF MANUFACTURING A THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE
    3.
    发明申请
    METHOD OF MANUFACTURING A THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20210375886A1

    公开(公告)日：2021-12-02

    申请号：US17398536

    申请日：2021-08-10

    申请人： SK hynix Inc.

    发明人： Eun Mee KWON ,  Da Som LEE

    IPC分类号： H01L27/1158 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11514 ,  H01L27/11553 ,  H01L27/11504 ,  H01L27/11509 ,  H01L27/11526

    摘要： 22In a method of manufacturing a non-volatile memory device, insulating layers and conductive gates may be alternately formed on a semiconductor substrate to form a stack structure. A contact hole may be formed through the stack structure. A channel layer may be formed on a surface of the contact hole. The contact hole may be filled with a gap-fill insulating layer. The gap-fill insulating layer may be etched by a target depth to define a preliminary junction region. The channel layer may be etched until a surface of the channel layer may correspond to a surface of an uppermost gate among the gates. Diffusion-preventing ions may be implanted into the channel layer. A capping layer with impurities may be formed in the preliminary junction region.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230140566A1

    公开(公告)日：2023-05-04

    申请号：US17730805

    申请日：2022-04-27

    申请人： SK hynix Inc.

    发明人： Sun Mi PARK ,  Eun Mee KWON ,  Hyung Jun YANG

    IPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L27/24

    摘要： There are provided a semiconductor device and a manufacturing method of a semiconductor device. The semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; channel structures penetrating the gate structure, the channel structures being arranged in a first direction; and a cutting structure extending in the first direction, the cutting structure consecutively penetrating the channel structures. Each of the channel structures includes a first channel structure and a second channel structure, which are isolated from each other by the cutting structure.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230380162A1

    公开(公告)日：2023-11-23

    申请号：US17989484

    申请日：2022-11-17

    申请人： SK hynix Inc.

    发明人： Yeon Seob IM ,  Eun Mee KWON ,  Nam Kuk KIM ,  Keon Soo SHIM

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11565

    摘要： A semiconductor memory device includes a first channel structure which is adjacent to an insulating structure and penetrates a plurality of conductive layers, a second channel structure which is spaced apart from the insulating structure and penetrates the plurality of conductive layers, a first impurity region included in an end portion of the first channel structure, and a second impurity region included in an end portion of the second channel structure. A doping concentration of an impurity in the first impurity region is different from a doping concentration of an impurity in the second impurity region.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220367485A1

    公开(公告)日：2022-11-17

    申请号：US17512047

    申请日：2021-10-27

    申请人： SK hynix Inc.

    发明人： Sun Mi PARK ,  Nam Kuk KIM ,  Eun Mee KWON ,  Sang Wan JIN

    IPC分类号： H01L27/1157 ,  H01L25/065 ,  H01L27/11582

    摘要： A semiconductor memory device, and a method of manufacturing the same, includes a lower stack in which a plurality of first interlayer insulating layers and first conductive layers are alternately stacked, a plurality of cell plugs passing through the lower stack in a vertical direction, an upper stack in which a plurality of second interlayer insulating layers and at least one second conductive layer are alternately stacked on the lower stack, a plurality of drain select plugs passing through the upper stack and being in contact with an upper portion of the plurality of cell plugs, and a separation pattern separating adjacent drain select plugs among the plurality of drain select plugs, wherein the separation pattern is in contact with a sidewall of each of the adjacent drain select plugs.