公开(公告)号：US10892262B2

公开(公告)日：2021-01-12

申请号：US16398118

申请日：2019-04-29

申请人： SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

发明人： Jung-Min Moon ,  Tae-Kyun Kim ,  Seok-Hee Lee

IPC分类号： H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423

摘要： A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

公开(公告)号：US10361206B2

公开(公告)日：2019-07-23

申请号：US14825030

申请日：2015-08-12

申请人： SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

发明人： Jung-Min Moon ,  Tae-Kyun Kim ,  Seok-Hee Lee

IPC分类号： H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423

摘要： A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

公开(公告)号：US08633752B2

公开(公告)日：2014-01-21

申请号：US13707460

申请日：2012-12-06

申请人： SK hynix Inc.

发明人： Tae-Kyun Kim

IPC分类号： H03K3/00

CPC分类号： H03H11/265 ,  H03K5/05 ,  H03K5/1534 ,  H03K2005/00293 ,  H03L7/06

摘要： A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal.

摘要翻译： 延迟电路包括：脉冲发生单元，被配置为产生响应于输入信号被激活并具有对应于延迟信息的脉冲宽度的脉冲信号;以及输出单元，被配置为响应于去激活而激活最终输出信号 的脉冲信号。

公开(公告)号：US10020073B2

公开(公告)日：2018-07-10

申请号：US15059057

申请日：2016-03-02

申请人： SK hynix Inc.

发明人： Tae-Kyun Kim ,  Jae-Il Kim ,  Hee-Seong Kim ,  Jun-Gi Choi

IPC分类号： G06F11/00 ,  G11C29/50 ,  G11C11/406 ,  G11C11/408 ,  G11C29/04 ,  G11C29/44

CPC分类号： G11C29/50016 ,  G11C11/40611 ,  G11C11/408 ,  G11C11/4087 ,  G11C2029/0409 ,  G11C2029/4402 ,  G11C2211/4061 ,  G11C2211/4062

摘要： A memory device may include: a plurality of memory cells; at least one address storage unit; a fail detection unit suitable for comparing first and second read data that are read from at least one memory cell selected among the plurality of memory cells to detect a fail, and storing an address of the selected memory cell in the address storage unit when the fail is detected; and a refresh control unit suitable for refreshing the memory cell corresponding to the address stored in the address storage unit at a higher frequency than the other memory cells.

公开(公告)号：US09136376B2

公开(公告)日：2015-09-15

申请号：US13759395

申请日：2013-02-05

申请人： SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

发明人： Jung-Min Moon ,  Tae-Kyun Kim ,  Seok-Hee Lee

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L27/10814 ,  H01L29/105 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7828

摘要： A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

摘要翻译： 无连接垂直栅晶体管包括从衬底垂直突出并包括顺序地形成在第一杂质区上的第一杂质区，第二杂质区和第三杂质区的有源柱; 耦合到第二杂质区的侧壁的栅电极; 以及沿着与栅电极交叉的方向排列的每一个与第一杂质区接触的位线。 第一至第三杂质区包括相同极性的杂质。

公开(公告)号：US10665279B2

公开(公告)日：2020-05-26

申请号：US16186367

申请日：2018-11-09

申请人： SK hynix Inc.

发明人： Tae-Kyun Kim

IPC分类号： G11C8/18 ,  G11C8/12 ,  G11C7/06 ,  G11C7/10 ,  G11C8/10

摘要： A memory device includes a memory bank; a first latch circuit positioned at the one side of the memory bank, for latching a first column address in synchronization with a first strobe signal; a second latch circuit positioned at the other side of the memory bank, for latching a second column address in synchronization with a second strobe signal; a first column decoder positioned at the one side of the memory bank, for generating first column select signals in synchronization with the first strobe signal and the first column address; and a second column decoder positioned at the other side of the memory bank, for generating second column select signals in synchronization with the second strobe signal and the second column address.

公开(公告)号：US10157685B2

公开(公告)日：2018-12-18

申请号：US15089230

申请日：2016-04-01

申请人： SK hynix Inc.

发明人： Tae-Kyun Kim ,  Jin-Hee Cho ,  Jun-Gi Choi

IPC分类号： G06F11/14 ,  G06F11/36 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/14 ,  G11C29/18 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G11C29/46 ,  G11C29/50

摘要： A memory device may include a plurality of memory cells; one or more backup memory cells; a test circuit suitable for performing a backup operation and a test operation to a test target cell selected among the plurality of memory cells; and a control circuit suitable for accessing the backup memory cells instead of the test target cell during the performance of the test operation after completion of the backup operation for the selected test target cell, wherein, during the backup operation, the test circuit controls the control circuit to copy an original data of the test target cell to a corresponding backup memory cell selected among the backup memory cells, and wherein, during the test operation, the test circuit determines whether the test target cell is a pass or a fail.

公开(公告)号：US10014071B2

公开(公告)日：2018-07-03

申请号：US15066773

申请日：2016-03-10

申请人： SK hynix Inc.

发明人： Min-Su Park ,  Jae-Il Kim ,  Tae-Kyun Kim ,  Jun-Gi Choi

IPC分类号： G11C29/08 ,  G11C11/406 ,  G11C11/4091 ,  G11C29/00

CPC分类号： G11C29/08 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4091 ,  G11C29/00 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/5002

摘要： A memory device may include a plurality of memory cells; an error detection unit suitable for: latching data read a first time from at least one selected memory cell of the plurality of memory cells in a detection period, comparing data read a second time from the at least one selected memory cell with the latched data, and detecting an error of the at least one selected memory cell in the detection when the date read a second time from the at least one substantially the same with the latched data.

公开(公告)号：US09589676B2

公开(公告)日：2017-03-07

申请号：US15056390

申请日：2016-02-29

申请人： SK hynix Inc.

发明人： Jun-Gi Choi ,  Tae-Kyun Kim

IPC分类号： G11C29/04 ,  G11C29/00 ,  G11C11/419 ,  G11C7/22

CPC分类号： G11C29/78 ,  G11C7/106 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4097 ,  G11C11/419 ,  G11C29/04 ,  G11C29/52 ,  G11C2207/229

摘要： A semiconductor device may include: a first latch configured to store data outputted from a memory cell during a first operation; and a fail detection circuit configured to detect a fail by comparing the data outputted from the memory cell to the data stored in the first latch through a second operation performed at a predetermined time after the first operation.

摘要翻译： 半导体器件可以包括：第一锁存器，被配置为在第一操作期间存储从存储器单元输出的数据; 以及故障检测电路，被配置为通过在第一操作之后的预定时间执行的第二操作来比较从存储器单元输出的数据与存储在第一锁存器中的数据来检测故障。

公开(公告)号：US10950608B2

公开(公告)日：2021-03-16

申请号：US16398109

申请日：2019-04-29

申请人： SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

发明人： Jung-Min Moon ,  Tae-Kyun Kim ,  Seok-Hee Lee

IPC分类号： H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423

摘要： A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.