公开(公告)号：US12126357B2

公开(公告)日：2024-10-22

申请号：US18085236

申请日：2022-12-20

Applicant: SK hynix Inc.

Inventor： Seon Woo Hwang ,  Seong Jin Kim ,  Jung Hwan Ji

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/1111 ,  H03M13/6356

Abstract: In an embodiment, an error correction code circuit is provided. The error correction code circuit includes an error correction code engine and data processing circuit. The error correction code engine is configured to generate a second parity signal and syndrome information by performing an operation on operation source data and a first parity signal. The data processing circuit is configured to output write data as the operation source data and output an internally generated dummy parity signal as the first parity signal during a write operation, and to output read data as the operation source data and output a read parity signal as the first parity signal during a read operation.

公开(公告)号：US09081515B2

公开(公告)日：2015-07-14

申请号：US13845586

申请日：2013-03-18

Applicant: SK hynix Inc.

Inventor： Jung Hwan Ji ,  Geun Il Lee

IPC: H03L7/00 ,  G06F1/08

CPC classification number: G06F1/08

Abstract: A clock generation circuit includes a counting code generation unit configured to generate counting codes corresponding to a frequency of an input clock when an enable signal is enabled; a control code generation unit configured to decode the counting codes and generate control codes; and a cycle changeable oscillation unit configured to determine a frequency of an output clock in response to the control codes.

Abstract translation: 时钟发生电路包括计数代码生成单元，被配置为当使能信号有效时产生与输入时钟的频率相对应的计数代码; 控制代码生成单元，被配置为对计数代码进行解码并生成控制代码; 以及循环可变振荡单元，其被配置为响应于所述控制代码来确定输出时钟的频率。

公开(公告)号：US10529425B2

公开(公告)日：2020-01-07

申请号：US16041559

申请日：2018-07-20

Applicant: SK hynix Inc.

Inventor： Jung Hwan Ji ,  Sang Ho Lee ,  Ho Don Jung ,  Jun Hyun Chun

IPC: G11C8/00 ,  G11C16/08 ,  G11C8/10 ,  G11C11/408 ,  G11C7/18 ,  G11C8/12 ,  G11C5/02 ,  G11C11/4097 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/4096

Abstract: A semiconductor apparatus may include a unit memory region, a first column main decoder, a second column main decoder, and a control circuit. The unit memory region may include a plurality of sub-memory regions. The first and second column main decoders may be configured to receive and decode a column pre-decoding signal and configured to generate a respective column select signal for controlling a column access of a respective first and second half of the plurality of sub-memory regions. The control circuit may be configured to provide the column pre-decoding signal to the first or second column main decoders based on their proximities to a sub-memory region to be enabled among the plurality of sub-memory regions.

公开(公告)号：US11967389B2

公开(公告)日：2024-04-23

申请号：US17737268

申请日：2022-05-05

Applicant: SK hynix Inc.

Inventor： Seon Woo Hwang ,  Seong Jin Kim ,  Jung Hwan Ji

IPC: G11C29/14 ,  G11C7/06 ,  G11C7/10 ,  G11C29/12 ,  G11C29/42 ,  G11C29/46

CPC classification number: G11C29/42 ,  G11C7/065 ,  G11C7/1069 ,  G11C7/1096 ,  G11C29/1201 ,  G11C29/46

Abstract: The present technology may include a first storage circuit connected to a plurality of memory banks, an error correction circuit, a read path including a plurality of sub-read paths connected between the plurality of memory banks and the error correction circuit, and a control circuit configured to control data output from the plurality of memory banks to be simultaneously stored in the first storage circuit by deactivating the read path during a first sub-test section, and to control the data stored in the first storage circuit to be sequentially transmitted to the error correction circuit by sequentially activating the plurality of sub-read paths during a second sub-test section.

公开(公告)号：US09564191B1

公开(公告)日：2017-02-07

申请号：US15047116

申请日：2016-02-18

Applicant: SK hynix Inc.

Inventor： Jung Hwan Ji ,  Ki Chon Park

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/08 ,  G11C7/12

CPC classification number: G11C7/222 ,  G11C7/08 ,  G11C7/12

Abstract: A signal compensation circuit includes a first path configured to cause a source signal to pass therethrough and be outputted as a first signal; a delay block configured to output a second signal by delaying the source signal by a predetermined time; a second path configured to cause the second signal to pass therethrough and be outputted as a third signal; and a signal combination block configured to generate a compensated signal by combining the first signal and the third signal.

Abstract translation: 信号补偿电路包括被配置为使源信号通过并作为第一信号输出的第一路径; 延迟块，被配置为通过将源信号延迟预定时间来输出第二信号; 第二路径，被配置为使第二信号通过并作为第三信号输出; 以及信号组合块，被配置为通过组合所述第一信号和所述第三信号来产生补偿信号。

公开(公告)号：US11983071B2

公开(公告)日：2024-05-14

申请号：US17882123

申请日：2022-08-05

Applicant: SK hynix Inc.

Inventor： Seon Woo Hwang ,  Seong Jin Kim ,  Jung Hwan Ji

IPC: G06F11/10

CPC classification number: G06F11/108

Abstract: The present technology may include an error correction code engine configured to generate a parity bit and syndrome information by performing an operation according to operation source data, and a data processing circuit configured to simultaneously output the parity bit and first delay data, which is generated by delaying input data by a first time according to a write operation, simultaneously output the syndrome information and second delay data, which is generated by delaying input data by a second time according to a read operation, and to share substantially the same signal path in generating the first delay data and in generating the second delay data.

公开(公告)号：US09800244B2

公开(公告)日：2017-10-24

申请号：US15086669

申请日：2016-03-31

Applicant: SK hynix Inc.

Inventor： Jung Ho Lim ,  Jung Hwan Ji

IPC: H03K19/003 ,  H03K19/20 ,  H03K5/06

CPC classification number: H03K19/00384 ,  H03K5/06 ,  H03K19/20

Abstract: An inverter circuit includes a pull-up control circuit and a pull-up drive circuit. The pull-up control circuit generates a drive signal which is enabled during a first time period in response to an input signal and an output signal. The pull-up drive circuit drives the output signal to a power supply voltage in response to the input signal and the drive signal. The pull-up drive unit drives the output signal with a first drivability during the first time period and drives the output signal with a second drivability during a second time period.