公开(公告)号：US20160197624A1

公开(公告)日：2016-07-07

申请号：US14988303

申请日：2016-01-05

Applicant: SK hynix memory solutions inc.

Inventor： Chung-Li Wang ,  Lingqi Zeng ,  Yi-Min Lin

IPC: H03M13/11

CPC classification number: H03M13/1108 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/23 ,  H03M13/2957 ,  H03M13/2963

Abstract: A method for decoding low-density parity check (LDPC) codes, includes computing an initial syndrome of an initial output, obtaining an initial number of unsatisfied checks based on the computed initial syndrome, and when the initial number of unsatisfied checks is greater than zero, computing a reliability value with a parity check, performing a bit flip operation, computing a subsequent syndrome of a subsequent output, and ending decoding when a number of unsatisfied checks obtained based on the computed subsequent syndrome is equal to zero.

Abstract translation: 用于解码低密度奇偶校验（LDPC）码的方法包括计算初始输出的初始综合征，基于所计算的初始综合征获得不满足的检查的初始数目，以及当初始不满足检查数大于零时 利用奇偶校验计算可靠性值，执行位翻转操作，计算随后输出的后续校正子，以及当基于所计算的后续校正子获得的多个不满足的检查值等于零时，结束解码。

公开(公告)号：US20160026526A1

公开(公告)日：2016-01-28

申请号：US14721888

申请日：2015-05-26

Applicant: SK hynix memory solutions inc.

Inventor： Fan Zhang ,  Chung-Li Wang ,  Chun Hok Ho

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F21/79 ,  G11C2029/0411

Abstract: A first physical location is read to obtain read data. Error correction decoding is performed on the read data to obtain error-corrected data where the error-corrected data includes first error-corrected metadata. Error correction encoding is performed on a first random sequence combined with a second random sequence, concatenated with second metadata. Error correction encoding is also performed on a sequence of zeros concatenated with the first error-corrected metadata to obtain second encoded data. The error-corrected data, the first encoded data, and the second encoded data are summed to obtain migrated data, which is stored at a second physical location.

Abstract translation: 读取第一个物理位置以获取读取数据。 对读取的数据执行错误校正解码以获得纠错数据，其中纠错数据包括第一纠错元数据。 对与第二随机序列组合的第一随机序列进行纠错编码，并与第二元数据连接。 还对与第一纠错元数据连接的零序列执行纠错编码，以获得第二编码数据。 纠错数据，第一编码数据和第二编码数据被相加以获得存储在第二物理位置的迁移数据。

公开(公告)号：US09906240B2

公开(公告)日：2018-02-27

申请号：US15173198

申请日：2016-06-03

Applicant: SK Hynix Memory Solutions Inc.

Inventor： Yi-Min Lin ,  Aman Bhatia ,  Naveen Kumar ,  Chung-Li Wang ,  Lingqi Zeng

IPC: H03M13/15 ,  H03M13/00 ,  H03M13/29

CPC classification number: H03M13/152 ,  H03M13/1525 ,  H03M13/1545 ,  H03M13/1575 ,  H03M13/2963 ,  H03M13/6502

Abstract: A decoder includes a syndrome generator for receiving a codeword and generating at least two syndromes based on the codeword, an error location polynomial generator for generating an error-location polynomial based on the syndromes, an error location determiner for determining at least one error location based on the error-location polynomial, and an error corrector for correcting the codeword based on the one error location. The error location polynomial generator includes a logic for receiving the syndromes and generating a combination of the syndromes as a combination of coefficients of the error-location polynomial, and a key equation solver for generating the error-location polynomial based on the combination of the coefficients and finding at least one root of the error-location polynomial. The error location determiner determines the error location based on a combination of the root and one of the syndromes.

公开(公告)号：US20180129430A1

公开(公告)日：2018-05-10

申请号：US15346103

申请日：2016-11-08

Applicant: SK Hynix Memory Solutions Inc.

Inventor： Jingyu Kang ,  Chung-Li Wang ,  Cai Wang ,  Yibo Zhang

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  H03M13/13 ,  H03M13/27

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0665 ,  G06F3/0679 ,  G06F11/1044 ,  G06F11/1068 ,  G11C29/52 ,  H03M13/13 ,  H03M13/2757

Abstract: Memory systems may include a memory storage including at least a first stripe and a second stripe, the first stripe including data pages corresponding to the first stripe and a first parity page suitable for storing a first XOR parity, and the second stripe including data pages corresponding to the second stripe and a second parity page suitable for storing a second XOR parity, the data pages and parity pages being stored over a plurality of memory dies, wherein each memory die includes a number of planes; and a controller suitable for cyclically interleaving the data pages corresponding to the first stripe and the data pages corresponding to the second stripe.