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    Manufacturing testing for LDPC codes
    2.
    发明授权
    Manufacturing testing for LDPC codes 有权

    公开(公告)号：US09875157B2

    公开(公告)日：2018-01-23

    申请号：US14298736

    申请日：2014-06-06

    Applicant: SK hynix memory solutions inc.

    Inventor： Yu Kou ,  Lingqi Zeng ,  Jason Bellorado ,  Marcus Marrow

    IPC: H03M13/00 ,  G06F11/10 ,  H03M13/11 ,  G06F11/08 ,  G11C29/56 ,  H03M13/01

    CPC classification number: G06F11/1076 ,  G06F11/08 ,  G06F11/1012 ,  G11C29/56004 ,  H03M13/015 ,  H03M13/1102 ,  H03M13/154

    Abstract: A storage system includes a channel detector, an LDPC decoder, and an erasure block. The channel detector is configured to receive data corresponding to data read from a storage and output an LLR signal. The LDPC decoder is configured to receive the LLR signal and output a feedback signal to the channel detector. The erasure block is configured to erase at a portion of at least one of the LLR signal and the feedback signal. A method for testing includes generating an error rate function corresponding to an erasure pattern. The function is a function of a number of LDPC iterations. The method includes determining testing parameters at least in part based on the error rate function, wherein the testing parameters comprise a testing number of LDPC iterations, a passing error rate, and the erasure pattern. The method includes testing storage devices using the testing parameters.

    Method and system for generating soft-information after a single read in NAND flash using expected and measured values
    3.
    发明授权
    Method and system for generating soft-information after a single read in NAND flash using expected and measured values 有权
    在NAND闪存中使用预期和测量值进行单次读取后生成软信息的方法和系统

    公开(公告)号：US09256522B1

    公开(公告)日：2016-02-09

    申请号：US13858781

    申请日：2013-04-08

    Applicant: SK hynix memory solutions inc.

    Inventor： Xiangyu Tang ,  Lingqi Zeng ,  Jason Bellorado ,  Frederick K. H. Lee ,  Arunkumar Subramanian

    IPC: G06F12/02 ,  G06F11/10 ,  G06F11/00 ,  G11C16/34 ,  G11C16/26 ,  G06F12/00

    CPC classification number: G06F12/00 ,  G06F11/008 ,  G06F11/1012 ,  G06F11/1072 ,  G06F12/0246 ,  G06F2212/1032 ,  G06F2212/2022 ,  G11C16/26 ,  G11C16/34

    Abstract: A system and method for determining soft read data for a group of cells in a nonvolatile flash memory are disclosed. An expected value representative of a plurality of stored values in a group of cells is obtained. A measured value representative of the plurality of stored values in the group of cells is obtained, based on a single read to the group of cells. A soft read data for the group of cells is determined based at least in part on the expected value and the measured value. The expected and measured values may include at least one of a number of 0s, a number of 1s, a ratio of 0s to 1s or a ratio of 1s to 0s. A reliability for a bit i may be obtained using a one-step majority logic decoder, and a threshold reliability may be used when determining the soft read data.

    Abstract translation: 公开了一种用于确定非易失性闪速存储器中的一组单元的软读取数据的系统和方法。 获得代表一组单元格中的多个存储值的期望值。 基于对单元格组的单次读取，获得表示该组单元格中的多个存储值的测量值。 至少部分地基于期望值和测量值确定该组单元的软读取数据。 期望值和测量值可以包括数量为0，数量1s，0s至1s的比率或1s至0s的比率中的至少一个。 使用一步多数逻辑解码器可以获得一位i的可靠性，并且当确定软读取数据时可以使用阈值可靠性。

    STORAGE OF READ THRESHOLDS FOR NAND FLASH STORAGE USING LINEAR APPROXIMATION
    5.
    发明申请
    STORAGE OF READ THRESHOLDS FOR NAND FLASH STORAGE USING LINEAR APPROXIMATION 审中-公开
    存储使用线性近似的NAND闪存存储读取阈值

    公开(公告)号：US20150085572A1

    公开(公告)日：2015-03-26

    申请号：US14553745

    申请日：2014-11-25

    Applicant: SK hynix memory solutions inc.

    Inventor： Arunkumar Subramanian ,  Xiangyu Tang ,  Jason Bellorado ,  Lingqi Zeng ,  Frederick K.H. Lee

    IPC: G11C16/26

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3404 ,  G11C16/349

    Abstract: A first read threshold associated with a first page in a block and a second read threshold associated with a second page in the block are received, where the first page has a first page number and the second page has a second page number. A slope and a y intercept are determined based at least in part on the first read threshold, the second read threshold, the first page number, and the second page number. The slope and the y intercept are stored with a block identifier associated with the block.

    Abstract translation: 接收与块中的第一页相关联的第一读取阈值和与块中的第二页相关联的第二读取阈值，其中第一页面具有第一页面编号，并且第二页面具有第二页面编号。 至少部分地基于第一读取阈值，第二读取阈值，第一页面编号和第二页面数量来确定斜率和y截距。 斜率和y截距用与块相关联的块标识符存储。

    Storage of read thresholds for NAND flash storage using linear approximation
    6.
    发明授权
    Storage of read thresholds for NAND flash storage using linear approximation 有权
    使用线性近似来存储NAND闪存的读取阈值

    公开(公告)号：US08923066B1

    公开(公告)日：2014-12-30

    申请号：US13852934

    申请日：2013-03-28

    Applicant: SK hynix memory solutions inc.

    Inventor： Arunkumar Subramanian ,  Xiangyu Tang ,  Jason Bellorado ,  Lingqi Zeng ,  Frederick K. H. Lee

    IPC: G11C16/26 ,  G11C29/00

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3404 ,  G11C16/349

    Abstract: A first read threshold associated with a first page in a block and a second read threshold associated with a second page in the block are received, where the first page has a first page number and the second page has a second page number. A slope and a y intercept are determined based at least in part on the first read threshold, the second read threshold, the first page number, and the second page number. The slope and the y intercept are stored with a block identifier associated with the block.

    Abstract translation: 接收与块中的第一页相关联的第一读取阈值和与块中的第二页相关联的第二读取阈值，其中第一页面具有第一页面编号，并且第二页面具有第二页面编号。 至少部分地基于第一读取阈值，第二读取阈值，第一页面编号和第二页面数量来确定斜率和y截距。 斜率和y截距用与块相关联的块标识符存储。

    Generating read thresholds using gradient descent and without side information
    7.
    发明授权
    Generating read thresholds using gradient descent and without side information 有权
    使用梯度下降和无旁边信息生成读取阈值

    公开(公告)号：US08923062B1

    公开(公告)日：2014-12-30

    申请号：US13935714

    申请日：2013-07-05

    Applicant: SK hynix memory solutions inc.

    Inventor： Frederick K. H. Lee ,  Jason Bellorado ,  Arunkumar Subramanian ,  Lingqi Zeng ,  Xiangyu Tang ,  Ameen Aslam

    IPC: G11C11/34 ,  G11C16/06

    CPC classification number: G11C16/26 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/3404

    Abstract: A next read threshold is determined by determining a first number of solid state storage cells having a stored voltage which falls into a first voltage range and determining a second number of solid state storage cells having a stored voltage which falls into a second voltage range. A gradient is determine by taking a difference between the first number of solid state storage cells and the second number of solid state storage cells. The next read threshold is determined based at least in part on the gradient.

    Abstract translation: 通过确定具有落入第一电压范围的存储电压的第一数量的固态存储单元并且确定具有落入第二电压范围的存储电压的第二数量的固态存储单元来确定下一个读取阈值。 通过取第一数量的固态存储单元和第二数量的固态存储单元之间的差来确定梯度。 至少部分地基于梯度来确定下一个读取阈值。

    TURBO-PRODUCT CODES (TPC) WITH INTERLEAVING
    8.
    发明申请
    TURBO-PRODUCT CODES (TPC) WITH INTERLEAVING 有权
    TURBO产品代码（TPC）具有交互性

    公开(公告)号：US20140129899A1

    公开(公告)日：2014-05-08

    申请号：US14061600

    申请日：2013-10-23

    Applicant: SK hynix memory solutions inc.

    Inventor： Naveen Kumar ,  Zheng Wu ,  Jason Bellorado ,  Lingqi Zeng ,  Marcus Marrow

    IPC: H03M13/27

    CPC classification number: H03M13/2918 ,  H03M13/2927 ,  H03M13/2963 ,  H03M13/2966

    Abstract: Decoding associated with a second error correction code and a first error correction code is performed. Ns first and second-corrected segments of data, first sets of parity information, and second sets of parity information are intersegment interleaved to obtain intersegment interleaved data, where the Ns segments of data, the Ns first sets of parity information, and the Ns second sets of parity information have had decoding associated with the first and the second error correction code performed on them (Ns is the number of segments interleaved together). Decoding associated with a third error correction code is performed on the intersegment interleaved data and interleaved parity information to obtain at least third-corrected interleaved data. The third-corrected interleaved data is de-interleaved.

    Abstract translation: 执行与第二纠错码和第一纠错码相关联的解码。 Ns个第一和第二校正的数据段，第一组奇偶校验信息和第二组奇偶校验信息被进行交插，以获得段间交织数据，其中Ns个数据段，N个第一组奇偶校验信息和Ns秒 奇偶校验信息组具有与对它们执行的第一和第二纠错码相关联的解码（Ns是交织在一起的段数）。 对段间交错数据和交错奇偶校验信息执行与第三纠错码相关联的解码，以获得至少第三校正交错数据。 第三校正的交错数据被解交织。

    One-shot decoder for two-error-correcting BCH codes
    9.
    发明授权
    One-shot decoder for two-error-correcting BCH codes 有权

    公开(公告)号：US09906240B2

    公开(公告)日：2018-02-27

    申请号：US15173198

    申请日：2016-06-03

    Applicant: SK Hynix Memory Solutions Inc.

    Inventor： Yi-Min Lin ,  Aman Bhatia ,  Naveen Kumar ,  Chung-Li Wang ,  Lingqi Zeng

    IPC: H03M13/15 ,  H03M13/00 ,  H03M13/29

    CPC classification number: H03M13/152 ,  H03M13/1525 ,  H03M13/1545 ,  H03M13/1575 ,  H03M13/2963 ,  H03M13/6502

    Abstract: A decoder includes a syndrome generator for receiving a codeword and generating at least two syndromes based on the codeword, an error location polynomial generator for generating an error-location polynomial based on the syndromes, an error location determiner for determining at least one error location based on the error-location polynomial, and an error corrector for correcting the codeword based on the one error location. The error location polynomial generator includes a logic for receiving the syndromes and generating a combination of the syndromes as a combination of coefficients of the error-location polynomial, and a key equation solver for generating the error-location polynomial based on the combination of the coefficients and finding at least one root of the error-location polynomial. The error location determiner determines the error location based on a combination of the root and one of the syndromes.

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