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公开(公告)号：US11159189B2
公开(公告)日：2021-10-26
申请号：US17108888
申请日：2020-12-01
IPC分类号： H04L7/04 , H04B1/04 , H03F1/02 , H03F3/19 , H03F3/24 , H03G3/30 , H04L7/00 , H03F3/00 , H03G3/00
摘要： A power amplifier module can include one or more switches, a coupler module, input signal pins, and a controller having first and second output terminals. The input signal pins can receive a voltage input/output signal, a clock input signal, and a data input signal. The controller can (i) set a mode of the one or more switches using a synchronous communication protocol in which the controller outputs a synchronous clock signal on the first output terminal and a data signal on the second output terminal, when the power amplifier module is in a first operating mode, or (ii) set a mode of the coupler module using an asynchronous communication protocol in which the controller outputs a first asynchronous control signal on the first output terminal and a second asynchronous control signal on the second output terminal, when the power amplifier module is in a second operating mode.
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公开(公告)号：US20190272251A1
公开(公告)日：2019-09-05
申请号：US16271441
申请日：2019-02-08
摘要： A simplified serial interface for a communications device. The serial interface includes an RF front end and a transmit block and at least one receive block located on different dies. The receive block is activated by a clock generator that is separate than the system clock. The at least one receive block can inhibit transmission of an enable signal to the receive block and inhibit operation of an oscillator of the interface.
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3.发明申请公开(公告)号：US20190222240A1
公开(公告)日：2019-07-18
申请号：US16246344
申请日：2019-01-11
IPC分类号： H04B1/04 , H04L7/04 , H03F1/02 , H03F3/19 , H03F3/24 , H04L7/00 , H03G3/00 , H03F3/00 , H03G3/30
CPC分类号： H04B1/0475 , H03F1/0222 , H03F3/00 , H03F3/19 , H03F3/24 , H03F3/245 , H03F2200/102 , H03F2200/111 , H03F2200/451 , H03G3/00 , H03G3/3042 , H04B1/0458 , H04B1/0483 , H04B2001/0408 , H04B2001/0433 , H04L7/0091 , H04L7/04
摘要： A power amplifier module can include one or more switches, a coupler module, input signal pins, and a controller having first and second output terminals. The input signal pins can receive a voltage input/output signal, a clock input signal, and a data input signal. The controller can (i) set a mode of the one or more switches using a synchronous communication protocol in which the controller outputs a synchronous clock signal on the first output terminal and a data signal on the second output terminal, when the power amplifier module is in a first operating mode, or (ii) set a mode of the coupler module using an asynchronous communication protocol in which the controller outputs a first asynchronous control signal on the first output terminal and a second asynchronous control signal on the second output terminal, when the power amplifier module is in a second operating mode.
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公开(公告)号：US09722771B2
公开(公告)日：2017-08-01
申请号：US15280885
申请日：2016-09-29
CPC分类号： H04B1/0475 , H03F1/0222 , H03F3/00 , H03F3/19 , H03F3/24 , H03F3/245 , H03F2200/102 , H03F2200/111 , H03F2200/451 , H03G3/00 , H03G3/3042 , H04B1/0458 , H04B1/0483 , H04B2001/0408 , H04B2001/0433 , H04L7/0091 , H04L7/04
摘要： A power amplifier module can include one or more switches, a coupler module, input signal pins, and a controller having first and second output terminals. The input signal pins can receive a voltage input/output signal, a clock input signal, and a data input signal. The controller can (i) set a mode of the one or more switches using a synchronous communication protocol in which the controller outputs a synchronous clock signal on the first output terminal and a data signal on the second output terminal, when the power amplifier module is in a first operating mode, or (ii) set a mode of the coupler module using an asynchronous communication protocol in which the controller outputs a first asynchronous control signal on the first output terminal and a second asynchronous control signal on the second output terminal, when the power amplifier module is in a second operating mode.
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公开(公告)号：US09473076B2
公开(公告)日：2016-10-18
申请号：US14534886
申请日：2014-11-06
发明人： Jianxing Ni , Michael Lynn Gerard , Ramanan Bairavasubramanian , Dwayne Allen Rowland , Matthew Lee Banowetz
CPC分类号： H03F1/32 , H03F3/19 , H03F3/191 , H03F3/195 , H03F3/211 , H03F3/245 , H03F2200/18 , H03F2200/451 , H03F2201/3215 , H03F2203/21127 , H03F2203/21145
摘要： Improved linearity performance for multi-mode power amplifiers. A power amplifier (PA) assembly can include a radio-frequency (RF) amplification path having a first stage and a second stage, with each stage including a transistor. The PA assembly can further include a biasing circuit having a first bias path between a supply node and the base of a corresponding transistor. The PA assembly can further include a linearizing circuit implemented as either or both of a second bias path and a coupling path relative to the first bias path. The second bias path can be configured to provide an additional base bias current to the base under a selected condition. The coupling path can be configured to improve linearity of the corresponding transistor operating in a first mode while allowing a ballast resistance to be sufficiently robust for the corresponding transistor operating in a second mode.
摘要翻译： 改进了多模功率放大器的线性性能。 功率放大器（PA）组件可以包括具有第一级和第二级的射频（RF）放大路径，每级包括晶体管。 PA组件还可以包括偏置电路，该偏置电路在供电节点和相应晶体管的基极之间具有第一偏置路径。 PA组件还可以包括实现为相对于第一偏置路径的第二偏置路径和耦合路径中的任一个或两者的线性化电路。 第二偏置路径可以被配置为在所选择的条件下向基座提供额外的基极偏置电流。 耦合路径可以被配置为改善以第一模式工作的相应晶体管的线性度，同时允许镇流电阻对于在第二模式中工作的相应晶体管足够稳健。
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公开(公告)号：US10248612B2
公开(公告)日：2019-04-02
申请号：US15280768
申请日：2016-09-29
摘要： A simplified serial interface for a communications device. The serial interface includes an RF front end and a transmit block and at least one receive block located on different dies. The receive block is activated by a clock generator that is separate than the system clock. The at least one receive block can inhibit transmission of an enable signal to the receive block and inhibit operation of an oscillator of the interface.
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公开(公告)号：US09774716B2
公开(公告)日：2017-09-26
申请号：US15388273
申请日：2016-12-22
CPC分类号： H04M1/24 , G01R31/282 , G01R31/2844 , H03F1/52 , H03F3/19 , H03F3/21 , H03F3/24 , H03F2200/426 , H03F2200/451 , H04M1/72569
摘要： According to one aspect, embodiments of the invention provide an overstress indicator circuit comprising a sense circuit configured to monitor a parameter of a device and generate a sense signal corresponding to the parameter, a detection circuit coupled to the sense circuit and configured to receive the sense signal from the sense circuit and generate a detection signal at a first level in response to a determination that the sense signal is indicative of an overstress condition in the device, an interface circuit, and a memory circuit coupled to the detection circuit and the interface circuit and configured to store an overstress condition indication for access via the interface circuit in response to receiving the detection signal at the first level.
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公开(公告)号：US09698853B2
公开(公告)日：2017-07-04
申请号：US14325314
申请日：2014-07-07
CPC分类号： H04B1/40 , H03F1/0233 , H03F1/52 , H03F3/191 , H03F3/24 , H03F3/245 , H03F2200/426 , H03F2200/441 , H03F2200/462 , H04B2001/0408
摘要： Various implementations include circuits, devices and/or methods that provide open loop current limiting power amplifiers and the like. In some implementations, an open loop current clamp includes a trim module to provide a control value and a limiting source having respective input and output terminals. The input terminal is coupled to the trim module to receive the control value. The output terminal coupled to a control terminal of the first transistor to provide a limiting electrical level produced in response to the control value by the limiting source. The limiting electrical level substantially setting a first mode of operation for the first transistor such that the current draw of the first transistor is substantially determined by the first mode of operation and the limiting electrical level such that a voltage at an output terminal of the first transistor exerts reduced influence on the current draw.
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公开(公告)号：US20170187857A1
公开(公告)日：2017-06-29
申请号：US15388273
申请日：2016-12-22
CPC分类号： H04M1/24 , G01R31/282 , G01R31/2844 , H03F1/52 , H03F3/19 , H03F3/21 , H03F3/24 , H03F2200/426 , H03F2200/451 , H04M1/72569
摘要： According to one aspect, embodiments of the invention provide an overstress indicator circuit comprising a sense circuit configured to monitor a parameter of a device and generate a sense signal corresponding to the parameter, a detection circuit coupled to the sense circuit and configured to receive the sense signal from the sense circuit and generate a detection signal at a first level in response to a determination that the sense signal is indicative of an overstress condition in the device, an interface circuit, and a memory circuit coupled to the detection circuit and the interface circuit and configured to store an overstress condition indication for access via the interface circuit in response to receiving the detection signal at the first level.
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公开(公告)号：US20170026136A1
公开(公告)日：2017-01-26
申请号：US15214727
申请日：2016-07-20
发明人： Philip H. Thompson , Steven T. Seiz , Roman Zbigniew Arkiszewski , Matthew Lee Banowetz , Duane A. Green
摘要： Disclosed herein are wireless transceivers with switches to reduce harmonic leakage. In some embodiments, a transmitter system includes a power amplification system including a first power amplifier configured to amplify a signal at a first cellular frequency band and a second power amplifier configured to amplify a signal at a second cellular frequency band. The transmitter includes a switch coupled between an output of the second power amplifier and a ground potential. The transmitter includes a controller configured to, based on a band select signal, control the switch and selectively enable or disable each of the first power amplifier and the second power amplifier. Selective control of the switch can reduce harmonic leakage compared to a system that does not include the disclosed switches and controls.
摘要翻译： 这里公开了具有减少谐波泄漏的开关的无线收发器。 在一些实施例中，发射机系统包括功率放大系统，功率放大系统包括配置成放大第一蜂窝频带的信号的第一功率放大器和被配置成在第二蜂窝频带放大信号的第二功率放大器。 发射机包括耦合在第二功率放大器的输出端和接地电位之间的开关。 发射机包括控制器，被配置为基于频带选择信号来控制开关并且选择性地启用或禁用第一功率放大器和第二功率放大器中的每个。 与不包括公开的开关和控制器的系统相比，开关的选择性控制可以减少谐波泄漏。
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