公开(公告)号：US10763194B2

公开(公告)日：2020-09-01

申请号：US15713389

申请日：2017-09-22

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics Pte Ltd

Inventor： Rennier Rodriguez ,  Bryan Christian Bacquian ,  Maiden Grace Maming ,  David Gani

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L21/683

Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.

公开(公告)号：US09177903B2

公开(公告)日：2015-11-03

申请号：US13853784

申请日：2013-03-29

Applicant: STMicroelectronics, Inc.

Inventor： Bernie Chrisanto Ang ,  Bryan Christian Bacquian

IPC: H01L21/00 ,  H01L23/498 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A method of assembling a multi-chip electronic device into a thin electronic package entails inverting a flip-chip die arrangement over a hollow substrate, stacking additional dies on the hollow substrate to form a multi-chip electronic device, and encapsulating the multi-chip electronic device. Containment of the encapsulant can be achieved by joining split substrate portions, or by reinforcing a hollow unitary substrate, using a removable adhesive film. Use of the removable adhesive film facilitates surrounding the multi-chip electronic device with the encapsulant. The adhesive film can also prevent encapsulant from creeping around the substrate to an underside of the substrate that supports solder ball pads for subsequent attachment to a ball grid array (BGA) or a land grid array (LGA).

Abstract translation: 将多芯片电子器件组装成薄电子封装的方法需要在中空衬底上反转倒装芯片布置，在中空衬底上堆叠另外的管芯以形成多芯片电子器件，并且封装多芯片 电子设备。 密封剂的封闭可以通过使用可移除的粘合剂膜连接分离的衬底部分或通过加强中空的整体衬底来实现。 使用可移除的粘合膜有助于用密封剂围绕多芯片电子器件。 粘合剂膜还可以防止密封剂在衬底周围爬行到支撑焊球垫的衬底的下侧，用于随后附接到球栅阵列（BGA）或焊盘栅阵列（LGA）。

公开(公告)号：US20170084490A1

公开(公告)日：2017-03-23

申请号：US14857965

申请日：2015-09-18

Applicant: STMICROELECTRONICS, INC.

Inventor： Bryan Christian Bacquian ,  Frederick Arellano ,  Aiza Marie Agudon

IPC: H01L21/78 ,  H01L21/66 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/29

CPC classification number: H01L21/02021 ,  H01L21/02035 ,  H01L21/56 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/12 ,  H01L23/293 ,  H01L23/3142 ,  H01L24/48 ,  H01L24/49 ,  H01L29/06 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/48225 ,  H01L2924/00014 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2224/45099

Abstract: A method is for making an integrated circuit (IC) device. The method may include dicing a wafer into IC dies, each IC die having an active surface, a back surface opposite the active surface, and a sidewall with a step defining a smaller periphery adjacent the back surface and a larger periphery adjacent the active surface. The method may include positioning a resin material between the back surface of each IC die and a respective substrate, and around each IC die so that the resin material abuts and is retained by the step.

公开(公告)号：US20190096788A1

公开(公告)日：2019-03-28

申请号：US15713389

申请日：2017-09-22

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics Pte Ltd

Inventor： Rennier Rodriguez ,  Bryan Christian Bacquian ,  Maiden Grace Maming ,  David Gani

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/683

Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.