公开(公告)号：US10796763B2

公开(公告)日：2020-10-06

申请号：US16256525

申请日：2019-01-24

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Francesco La Rosa ,  Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/08 ,  G11C16/32 ,  G11C16/30 ,  G11C16/10

Abstract: A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value.

公开(公告)号：US09876122B2

公开(公告)日：2018-01-23

申请号：US15365768

申请日：2016-11-30

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L29/788 ,  G11C16/04 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11553 ,  G11C16/14 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3213 ,  H01L27/11524 ,  H01L27/11521 ,  H01L27/11556

CPC classification number: H01L29/7883 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/788

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

公开(公告)号：US09543311B2

公开(公告)日：2017-01-10

申请号：US14625356

申请日：2015-02-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  G11C16/14 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L21/266 ,  H01L21/3213

CPC classification number: H01L29/7883 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/788

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

Abstract translation: 各种实施例提供了一种存储单元，其包括垂直选择栅极，在衬底上方延伸的浮置栅极，其中浮置栅极还在非零重叠距离上延伸在垂直选择栅极的一部分上方，存储器单元包括掺杂 注入在与选择栅极相对延伸的垂直沟道区域和与浮动栅极相对延伸的水平沟道区域的交点处的区域。

公开(公告)号：US20200274722A1

公开(公告)日：2020-08-27

申请号：US16783631

申请日：2020-02-06

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier

IPC: H04L9/32 ,  G06F21/72 ,  G06F21/60 ,  G11C16/04 ,  G11C16/28 ,  G11C16/10 ,  G11C16/30

Abstract: In accordance with an embodiment, a physically unclonable function device includes a set of transistor pairs, transistors of the set of transistor pairs having a randomly distributed effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of transistors of transistor pairs of the set of transistor pairs, and to identify a transistor pair in which the measured threshold difference is smaller than a margin value as being an unreliable transistor pair; and a write circuit configured to shift the effective threshold voltage of a transistor of the unreliable transistor pair to be inside the common random distribution.

公开(公告)号：US10192999B2

公开(公告)日：2019-01-29

申请号：US15852826

申请日：2017-12-22

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L29/788 ,  G11C16/04 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11553 ,  G11C16/14 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3213 ,  H01L27/11524 ,  H01L27/11521 ,  H01L27/11556

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.