公开(公告)号：US11387194B2

公开(公告)日：2022-07-12

申请号：US15930217

申请日：2020-05-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Fabrice Marinet ,  Julien Delalleau

IPC: H01L23/00 ,  G06F21/55

Abstract: A semiconductor substrate has a front face and a back face. A first contact and a second contact, spaced apart from each other, are located on the front face. An electrically conductive wafer is located on the back face. A detection circuit is configured to detect a thinning of the substrate from the back face. The detection circuit including a measurement circuit that takes a measurement of a resistive value of the substrate between said at least one first contact, said at least one second contact and said electrically conductive wafer. Thinning is detected in response to the measured resistive value.

公开(公告)号：US20210036126A1

公开(公告)日：2021-02-04

申请号：US16939767

申请日：2020-07-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Franck JULIEN

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/027 ,  H01L29/78

Abstract: In fabricating metal-oxide-semiconductor field-effect transistors (MOSFETs), the implanting of lightly doped drain regions is performed before forming gate regions with a physical gate length that is associated with a reference channel length. The step of implanting lightly doped drain regions includes forming an implantation mask defining the lightly doped drain regions and an effective channel length of each MOSFET. The forming of the implantation mask is configured to define an effective channel length of at least one MOSFET that is different from the respective reference channel length.

公开(公告)号：US10797158B2

公开(公告)日：2020-10-06

申请号：US16036453

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Christian Rivero

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28

Abstract: A MOS transistor is produced on and in an active zone and included a source region and a drain region. The active zone has a width measured transversely to a source-drain direction. A conductive gate region of the MOS transistor includes a central zone and, at a foot of the central zone, at least one stair that extends beyond the central zone along at least an entirety of the width of the active zone.

公开(公告)号：US20190295648A1

公开(公告)日：2019-09-26

申请号：US16441378

申请日：2019-06-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau

IPC: G11C16/04 ,  H01L29/423 ,  G11C16/14 ,  G11C16/12 ,  H01L27/11556 ,  H01L27/11521 ,  G11C16/26

Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.

公开(公告)号：US09978847B2

公开(公告)日：2018-05-22

申请号：US15454184

申请日：2017-03-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Christian Rivero

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L29/08

CPC classification number: H01L29/4236 ,  H01L21/02236 ,  H01L21/28167 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78

Abstract: An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate.

公开(公告)号：US09224482B2

公开(公告)日：2015-12-29

申请号：US14528780

申请日：2014-10-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Julien Delalleau

IPC: G11C16/00 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  H01L29/788 ,  H01L27/115 ,  H01L29/423

CPC classification number: G11C16/10 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34 ,  G11C16/3418 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7881

Abstract: The present disclosure relates to a memory comprising at least one word line comprising a row of split gate memory cells each comprising a selection transistor section comprising a selection gate and a floating-gate transistor section comprising a floating gate and a control gate. According to the present disclosure, the memory comprises a source plane common to the memory cells of the word line, to collect programming currents passing through memory cells during their programming, and the selection transistor sections of the memory cells are connected to the source plane. A programming current control circuit is configured to control the programming current passing through the memory cells by acting on a selection voltage applied to a selection line.

Abstract translation: 本公开涉及包括至少一个字线的存储器，该字线包括一行分离栅极存储单元，每行分离栅极存储单元包括选择晶体管部分，该选择晶体管部分包括选择栅极和包括浮置栅极和控制栅极的浮动栅极晶体管部分。 根据本公开，存储器包括与字线的存储器单元共同的源平面，以在编程期间收集通过存储器单元的编程电流，并且存储器单元的选择晶体管部分连接到源极平面。 编程电流控制电路被配置为通过作用于施加到选择线的选择电压来控制通过存储器单元的编程电流。

公开(公告)号：US12051656B2

公开(公告)日：2024-07-30

申请号：US18095136

申请日：2023-01-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Christian Rivero

IPC: H01L23/528 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/8234 ,  H01L23/00 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L23/573 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/45 ,  H01L29/4916

Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

公开(公告)号：US11943931B2

公开(公告)日：2024-03-26

申请号：US17220286

申请日：2021-04-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Quentin Hubert ,  Abderrezak Marzaki ,  Julien Delalleau

IPC: H10B43/35 ,  G11C5/06 ,  H10B43/10

CPC classification number: H10B43/35 ,  G11C5/063 ,  H10B43/10

Abstract: In one embodiment, a non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.

公开(公告)号：US10991710B2

公开(公告)日：2021-04-27

申请号：US16391768

申请日：2019-04-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Quentin Hubert ,  Abderrezak Marzaki ,  Julien Delalleau

IPC: H01L27/1157 ,  G11C5/06 ,  H01L27/11565

Abstract: A non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.

公开(公告)号：US10403730B2

公开(公告)日：2019-09-03

申请号：US15914846

申请日：2018-03-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Julien Delalleau

IPC: H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11521 ,  G11C16/14 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11524 ,  H01L29/78 ,  G11C16/04 ,  H01L21/306

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.