公开(公告)号：US11749343B2

公开(公告)日：2023-09-05

申请号：US17578086

申请日：2022-01-18

申请人： STMICROELECTRONICS INTERNATIONAL N.V.

发明人： Nitin Chawla ,  Tanmoy Roy ,  Anuj Grover

IPC分类号： G11C13/00 ,  G06F9/50 ,  G11C29/00 ,  G11C29/26 ,  G11C29/44 ,  G06N3/063

CPC分类号： G11C13/004 ,  G06F9/5016 ,  G06N3/063 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  G11C29/006 ,  G11C29/26 ,  G11C2029/4402 ,  G11C2211/561

摘要： A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.

公开(公告)号：US11895839B2

公开(公告)日：2024-02-06

申请号：US17675826

申请日：2022-02-18

申请人： Kioxia Corporation

发明人： Hideto Takekida

IPC分类号： H10B43/27 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  H10B41/27 ,  G11C16/04 ,  H10B41/35 ,  H10B43/35

CPC分类号： H10B43/27 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  G11C2211/561

摘要： A semiconductor storage device includes a stack, a channel layer, a first charge storage portion, and a second charge storage portion. The stack includes a plurality of conductive layers and a plurality of insulating layers, and the plurality of conductive layers and the plurality of insulating layers are alternately stacked one by one in a first direction. The channel layer extends in the first direction in the stack. The first charge storage portion is provided between the channel layer and each of the plurality of conductive layers in a second direction intersecting with the first direction. The second charge storage portion includes a portion interposed between two adjacent conductive layers in the plurality of conductive layers in the first direction.

公开(公告)号：US11676679B2

公开(公告)日：2023-06-13

申请号：US17470265

申请日：2021-09-09

申请人： Micron Technology, Inc.

发明人： Sanjay Subbarao ,  James Fitzpatrick

IPC分类号： G11C29/42 ,  G11C29/44 ,  G11C11/56 ,  H03M13/11

CPC分类号： G11C29/42 ,  G11C11/5635 ,  G11C11/5642 ,  G11C29/44 ,  H03M13/1105 ,  G11C2211/561

摘要： A memory sub-system configured to encode data using an error correcting code and an erasure code for storing data into memory cells and to decode data retrieved from the memory cells. For example, the data units of a predetermined size are separately encoded using the error correcting code (e.g., a low-density parity-check (LDPC) code) to generate parity data of a first layer. Symbols within the data units are cross encoded using the erasure code. Parity symbols of a second layer are calculated according to the erasure code. A collection of parity symbols having a total size equal to the predetermined size can be further encoded using the error correcting code to generate parity data for the parity symbols.

公开(公告)号：US11699491B2

公开(公告)日：2023-07-11

申请号：US17247643

申请日：2020-12-18

申请人： Micron Technology, Inc.

发明人： Phong Sy Nguyen ,  James Fitzpatrick ,  Kishore Kumar Muchherla

IPC分类号： G11C16/20 ,  G11C16/30 ,  G11C16/26

CPC分类号： G11C16/20 ,  G11C16/26 ,  G11C16/30 ,  G11C2211/561

摘要： Control logic in a memory device identifies a first plurality of groups of programming distributions, wherein each group comprises a subset of programming distributions associated with a portion of a memory array of the memory device configured as quad-level (QLC) memory. During a first pass of a multi-pass programming operation, the control logic coarsely programs memory cells in the portion configured as QLC memory to initial values representing a second plurality of pages of host data and stores, in a portion of the memory array of the memory device configured as single-level cell (SLC) memory, an indicator of the first plurality of groups of programming distributions with which each of the coarsely programmed memory cells is associated. During a second pass of the multi-pass programming operation, the control logic reads the coarsely programmed initial values from the first pass based on the indicator of the first plurality of groups of programming distributions and finely programs the memory cells in the portion configured as QLC memory to final values representing the second plurality of pages of host data.

公开(公告)号：US20190043563A1

公开(公告)日：2019-02-07

申请号：US16146814

申请日：2018-09-28

申请人： Ali Khakifirooz ,  Pranav Kalavade ,  Uday Chandrasekhar ,  Trupti Bemalkhedkar ,  Chang Wan Ha

发明人： Ali Khakifirooz ,  Pranav Kalavade ,  Uday Chandrasekhar ,  Trupti Bemalkhedkar ,  Chang Wan Ha

IPC分类号： G11C11/56

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/561 ,  G11C2211/5621

摘要： An apparatus and/or system is described including a memory device or a controller to perform programming and verification operations including application of a shared voltage level to verify two program voltage levels of a multi-level cell device. For example, in embodiments, the control circuitry performs a program operation to program a memory cell and performs a verification operation by applying a single or shared verify voltage level to verify that the memory cell is programmed to a corresponding program voltage level. In embodiments, the program voltage level is one of two consecutive program voltage levels of a plurality of program voltage levels to be verified by application of the shared verify voltage. Other embodiments are disclosed and claimed.