公开(公告)号：US10148810B2

公开(公告)日：2018-12-04

申请号：US15045935

申请日：2016-02-17

Applicant: STMicroelectronics (Tours) SAS

Inventor： Jean-Michel Simonnet ,  Christian Ballon

IPC: H04M1/74 ,  H01L27/02 ,  H02H9/04 ,  H04M3/18 ,  H04M3/00 ,  H04M19/08

Abstract: A structure protects a SLIC telephone line interface against overvoltages lower than a negative threshold or higher than a positive threshold. The structure includes at least one thyristor connected between each conductor of the telephone line and a reference potential. For all of the included thyristors, a metallization corresponding to the main electrode on the gate side is in contact, by its entire surface, with a corresponding semiconductor region. Furthermore, the gate of each thyristor is directly connected to a voltage source defining one of the thresholds.

公开(公告)号：US09685778B2

公开(公告)日：2017-06-20

申请号：US14725342

申请日：2015-05-29

Applicant: STMicroelectronics (Tours) SAS

Inventor： Mathieu Rouviere ,  Laurent Moindron ,  Christian Ballon

IPC: H02H3/20 ,  H01L29/732 ,  H01L27/07 ,  H01L29/87 ,  H01L27/02 ,  H01L27/06 ,  H01L49/02 ,  H01L29/739 ,  H01L29/78 ,  H01L29/872

CPC classification number: H02H3/20 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/0629 ,  H01L27/0761 ,  H01L28/20 ,  H01L29/732 ,  H01L29/7322 ,  H01L29/7395 ,  H01L29/7827 ,  H01L29/87 ,  H01L29/872

Abstract: An integrated circuit includes a vertical Shockley diode and a first vertical transistor. The diode is formed by, from top to bottom of a semiconductor substrate, a first region of a first conductivity type, a substrate of a second conductivity type, and a second region of the first conductivity type having a third region of the second conductivity type formed therein. The vertical transistor is formed by, also from top to bottom, a portion of the second region and a fourth region of the second conductivity type. The third and fourth regions are electrically connected to each other.

公开(公告)号：US20170019526A1

公开(公告)日：2017-01-19

申请号：US15045935

申请日：2016-02-17

Applicant: STMicroelectronics (Tours) SAS

Inventor： Jean-Michel Simonnet ,  Christian Ballon

IPC: H04M1/74 ,  H04M19/08 ,  H04M3/00 ,  H02H9/04

CPC classification number: H04M1/745 ,  H01L27/0248 ,  H01L27/0262 ,  H01L29/0638 ,  H01L29/74 ,  H02H9/041 ,  H02H9/043 ,  H04M3/005 ,  H04M3/18 ,  H04M19/08 ,  H04M2201/80

Abstract: A structure protects a SLIC telephone line interface against overvoltages lower than a negative threshold or higher than a positive threshold. The structure includes at least one thyristor connected between each conductor of the telephone line and a reference potential. For all of the included thyristors, a metallization corresponding to the main electrode on the gate side is in contact, by its entire surface, with a corresponding semiconductor region. Furthermore, the gate of each thyristor is directly connected to a voltage source defining one of the thresholds.

Abstract translation: 结构保护SLIC电话线接口免于低于负阈值或高于正阈值的过电压。 该结构包括连接在电话线的每个导体和参考电位之间的至少一个晶闸管。 对于所有包括的晶闸管，对应于栅极侧的主电极的金属化通过其整个表面与相应的半导体区域接触。 此外，每个晶闸管的栅极直接连接到限定其中一个阈值的电压源。

公开(公告)号：US20150380925A1

公开(公告)日：2015-12-31

申请号：US14725342

申请日：2015-05-29

Applicant: STMicroelectronics (Tours) SAS

Inventor： Mathieu Rouviere ,  Laurent Moindron ,  Christian Ballon

IPC: H02H3/20 ,  H01L27/06 ,  H01L27/02 ,  H01L29/739 ,  H01L49/02 ,  H01L29/872 ,  H01L29/78

CPC classification number: H02H3/20 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/0629 ,  H01L27/0761 ,  H01L28/20 ,  H01L29/732 ,  H01L29/7322 ,  H01L29/7395 ,  H01L29/7827 ,  H01L29/87 ,  H01L29/872

Abstract: An integrated circuit includes a vertical Shockley diode and a first vertical transistor. The diode is formed by, from top to bottom of a semiconductor substrate, a first region of a first conductivity type, a substrate of a second conductivity type, and a second region of the first conductivity type having a third region of the second conductivity type formed therein. The vertical transistor is formed by, also from top to bottom, a portion of the second region and a fourth region of the second conductivity type. The third and fourth regions are electrically connected to each other.

Abstract translation: 集成电路包括垂直Shockley二极管和第一垂直晶体管。 二极管由半导体衬底的顶部到底部形成第一导电类型的第一区域，第二导电类型的衬底和具有第二导电类型的第三区域的第一导电类型的第二区域 在其中形成。 垂直晶体管也是从顶部到底部形成第二区域的一部分和第二导电类型的第四区域。 第三和第四区域彼此电连接。