公开(公告)号：US09286160B2

公开(公告)日：2016-03-15

申请号：US14175843

申请日：2014-02-07

Applicant: STMicroelectronics International NV ,  STMicroelectronics S.r.l.

Inventor： BharathManoj Manda ,  Abhishek Lal ,  Marco Pasotti ,  Marcella Carissimi

IPC: G11C11/00 ,  G06F11/10 ,  G11C13/00

CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2029/0411 ,  G11C2211/5646

Abstract: According to embodiments, a phase change memory (PCM) array includes a plurality of memory cells grouped into memory blocks. In the PCM array, each memory cell is a PCM cell. The PCM array also includes a plurality of erase flag cells. Each erase flag cell of the plurality of erase flag cells is associated with a memory block and indicates whether the memory block stores valid data or erased data.

Abstract translation: 根据实施例，相变存储器（PCM）阵列包括分组成存储块的多个存储器单元。 在PCM阵列中，每个存储单元是PCM单元。 PCM阵列还包括多个擦除标志单元。 多个擦除标志单元的每个擦除标志单元与存储块相关联，并且指示存储器块是否存储有效数据或擦除的数据。

公开(公告)号：US20150228338A1

公开(公告)日：2015-08-13

申请号：US14175843

申请日：2014-02-07

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics International NV

Inventor： BharathManoj Manda ,  Abhishek Lal ,  Marco Pasotti ,  Marcella Carissimi

IPC: G11C13/00 ,  G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2029/0411 ,  G11C2211/5646

Abstract: According to embodiments, a phase change memory (PCM) array includes a plurality of memory cells grouped into memory blocks. In the PCM array, each memory cell is a PCM cell. The PCM array also includes a plurality of erase flag cells. Each erase flag cell of the plurality of erase flag cells is associated with a memory block and indicates whether the memory block stores valid data or erased data.

Abstract translation: 根据实施例，相变存储器（PCM）阵列包括分组成存储块的多个存储器单元。 在PCM阵列中，每个存储单元是PCM单元。 PCM阵列还包括多个擦除标志单元。 多个擦除标志单元的每个擦除标志单元与存储块相关联，并且指示存储器块是否存储有效数据或擦除的数据。

公开(公告)号：US20160099033A1

公开(公告)日：2016-04-07

申请号：US14506865

申请日：2014-10-06

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Abhishek Lal ,  Vikas Rana ,  Marco Pasotti

IPC: G11C8/10 ,  G11C8/18 ,  G11C7/22 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C8/10 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22

Abstract: A memory includes a column decoder performing at least two levels of decoding using a first level decoder that decodes between the column bit lines and first level decode lines and a second level decoder that decodes between the first level decode lines and second level decode lines. The second level decoder includes first transistors coupled between the first level decode lines and read output lines and second transistors coupled between the first level decode lines and write input lines. The first transistors have a first voltage rating and are driven by decode control signals referenced to a low supply voltage compatible with the first voltage rating. The second transistors have a second voltage rating, higher than the first voltage rating, and are driven by decode control signals referenced to a high supply voltage (in excess of the low supply voltage) compatible with the second voltage rating.

Abstract translation: 存储器包括列解码器，其使用在列位线和第一电平解码线之间解码的第一电平解码器和在第一电平解码线和第二电平解码线之间解码的第二电平解码器来执行解码的至少两个级别。 第二电平解码器包括耦合在第一电平解码线和读出输出线之间的第一晶体管和耦合在第一电平解码线和写输入线之间的第二晶体管。 第一晶体管具有第一电压额定值，并且由与第一额定电压兼容的低电源电压参考的解码控制信号驱动。 第二晶体管具有高于第一电压额定值的第二电压额定值，并且由与第二额定电压兼容的高电源电压（超过低电源电压）的解码控制信号驱动。

公开(公告)号：US20150235686A1

公开(公告)日：2015-08-20

申请号：US14183225

申请日：2014-02-18

Applicant: STMICROELECTRONICS S.R.L ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Marco Pasotti ,  Abhishek Lal ,  Rajat Kulshrestha

IPC: G11C8/10 ,  G11C8/08 ,  G11C8/06

CPC classification number: G11C8/10 ,  G11C8/06 ,  G11C8/08 ,  G11C16/12

Abstract: According to various embodiments described herein, a circuit includes a decode logic circuit, a buffer coupled to the decode logic, a positive level shifter with an input coupled to receive address signals and an output coupled to the buffer, and a negative level shifter with an input coupled to receive the address signals and an output coupled to the buffer.

Abstract translation: 根据本文描述的各种实施例，电路包括解码逻辑电路，耦合到解码逻辑的缓冲器，具有耦合以接收地址信号的输入和耦合到缓冲器的输出的正电平移位器，以及负电平移位器，具有 输入耦合以接收地址信号和耦合到缓冲器的输出。

公开(公告)号：US09324399B2

公开(公告)日：2016-04-26

申请号：US14183225

申请日：2014-02-18

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l

Inventor： Marco Pasotti ,  Abhishek Lal ,  Rajat Kulshrestha

IPC: G11C8/10 ,  G11C8/08 ,  G11C8/06 ,  G11C16/12

CPC classification number: G11C8/10 ,  G11C8/06 ,  G11C8/08 ,  G11C16/12

Abstract: According to various embodiments described herein, a circuit includes a decode logic circuit, a buffer coupled to the decode logic, a positive level shifter with an input coupled to receive address signals and an output coupled to the buffer, and a negative level shifter with an input coupled to receive the address signals and an output coupled to the buffer.

Abstract translation: 根据本文描述的各种实施例，电路包括解码逻辑电路，耦合到解码逻辑的缓冲器，具有耦合以接收地址信号的输入和耦合到缓冲器的输出的正电平移位器，以及负电平移位器，具有 输入耦合以接收地址信号和耦合到缓冲器的输出。