-
公开(公告)号：US09286160B2
公开(公告)日：2016-03-15
申请号：US14175843
申请日：2014-02-07
Inventor： BharathManoj Manda , Abhishek Lal , Marco Pasotti , Marcella Carissimi
CPC classification number: G06F11/1076 , G06F11/1048 , G11C13/0004 , G11C13/0069 , G11C13/0097 , G11C2029/0411 , G11C2211/5646
Abstract: According to embodiments, a phase change memory (PCM) array includes a plurality of memory cells grouped into memory blocks. In the PCM array, each memory cell is a PCM cell. The PCM array also includes a plurality of erase flag cells. Each erase flag cell of the plurality of erase flag cells is associated with a memory block and indicates whether the memory block stores valid data or erased data.
Abstract translation: 根据实施例，相变存储器（PCM）阵列包括分组成存储块的多个存储器单元。 在PCM阵列中，每个存储单元是PCM单元。 PCM阵列还包括多个擦除标志单元。 多个擦除标志单元的每个擦除标志单元与存储块相关联，并且指示存储器块是否存储有效数据或擦除的数据。
-
公开(公告)号：US20150228338A1
公开(公告)日：2015-08-13
申请号：US14175843
申请日：2014-02-07
Inventor： BharathManoj Manda , Abhishek Lal , Marco Pasotti , Marcella Carissimi
CPC classification number: G06F11/1076 , G06F11/1048 , G11C13/0004 , G11C13/0069 , G11C13/0097 , G11C2029/0411 , G11C2211/5646
Abstract: According to embodiments, a phase change memory (PCM) array includes a plurality of memory cells grouped into memory blocks. In the PCM array, each memory cell is a PCM cell. The PCM array also includes a plurality of erase flag cells. Each erase flag cell of the plurality of erase flag cells is associated with a memory block and indicates whether the memory block stores valid data or erased data.
Abstract translation: 根据实施例，相变存储器（PCM）阵列包括分组成存储块的多个存储器单元。 在PCM阵列中，每个存储单元是PCM单元。 PCM阵列还包括多个擦除标志单元。 多个擦除标志单元的每个擦除标志单元与存储块相关联，并且指示存储器块是否存储有效数据或擦除的数据。
-
公开(公告)号：US11942144B2
公开(公告)日：2024-03-26
申请号：US17582675
申请日：2022-01-24
Inventor： Marco Pasotti , Marcella Carissimi , Antonio Gnudi , Eleonora Franchi Scarselli , Alessio Antolini , Andrea Lico
IPC: G11C11/4096 , G06F7/544 , G11C11/4074 , G11C11/4076 , G11C11/408 , G11C11/4094
CPC classification number: G11C11/4096 , G06F7/5443 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4094
Abstract: A circuit includes a memory array with memory cells arranged in a matrix of rows and columns, where each row includes a word line connected to the memory cells of the row, and each column includes a bit line connected to the memory cells of the column. Computational weights for an in-memory compute operation (IMCO) are stored in the memory cells. A word line control circuit simultaneously actuates word lines in response to input signals providing coefficient data for the IMCO by applying word line signal pulses. A column processing circuit connected to the bit lines processes analog signals developed on the bit lines in response to the simultaneous actuation of the word lines to generate multiply and accumulate output signals for the IMCO. Pulse widths of the signal pulses are modulated to compensate for cell drift. The IMCO further handles positive/negative calculation for the coefficient data and computational weights.
-
公开(公告)号：US11189343B2
公开(公告)日：2021-11-30
申请号：US16940837
申请日：2020-07-28
Applicant: STMicroelectronics S.r.l.
Inventor： Laura Capecchi , Marco Pasotti , Marcella Carissimi , Riccardo Zurla
Abstract: A current-generator circuit includes an output-current generator circuit having a control branch to be coupled to a control current generator and adapted to provide a control current pulse and a driver electrically coupled between the control branch and the output leg. A compensation circuit includes a first compensation branch configured to generate a compensation current pulse that is a function of the control current pulse and a second compensation branch coupled in a current mirror configuration with the first compensation branch to receive the compensation current pulse. The second compensation branch includes a resistive block having an electrical resistance that is a function of a resistance of an output load. The second compensation branch is electrically coupled to the control branch and the driver is electrically coupled to the control branch and to the output leg.
-
公开(公告)号：US11133064B2
公开(公告)日：2021-09-28
申请号：US16931335
申请日：2020-07-16
Applicant: STMicroelectronics S.r.l.
Inventor： Marcella Carissimi , Laura Capecchi , Marco Pasotti , Fabio Enrico Carlo Disegni
Abstract: A sense amplifier and a method for accessing a memory device are disclosed. In an embodiment a sense amplifier for a memory device includes a first input node selectively coupled to a first memory cell through a first local bitline and a first main bitline, a second input node selectively coupled through a second local bitline and a second main bitline to a second memory cell or to a reference generator configured to generate a reference current, a first current generator controllable so as to inject a first variable current into the first input node, a second current generator controllable so as to inject a second variable current into the second input node, a first branch coupled to the first input node and comprising a first switch circuit, a first sense transistor and a first forcing transistor and a second branch coupled to the second input node and including a second switch circuit, a second sense transistor and a second forcing transistor.
-
Patent Agency Ranking
公开(公告)号：US10319438B2
公开(公告)日：2019-06-11
申请号：US15797860
申请日：2017-10-30
Applicant: STMicroelectronics S.r.l.
Inventor： Emanuela Calvetti , Marcella Carissimi , Marco Pasotti
Abstract: In accordance with an embodiment, a memory includes: a memory element, a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current, and a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current.
-
公开(公告)号：US20180330787A1
公开(公告)日：2018-11-15
申请号：US16044280
申请日：2018-07-24
Inventor： Marco Pasotti , Marcella Carissimi , Vikas Rana
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0026 , G11C2013/0078
Abstract: A method is provided for operating a memory device that includes an array of memory cells coupled to a plurality of bitlines. A memory cell is selected from among the array of memory cells. The selected memory cell is coupled to a selected bitline. During a program operation, a program current pulse is injected into the selected memory cell via a first switch coupled to the bitline. At an end of the program current pulse, the selected bitline is discharged via a second switch coupled to the bitline.
-
公开(公告)号：US09921598B1
公开(公告)日：2018-03-20
申请号：US15397137
申请日：2017-01-03
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Pasotti , Laura Capecchi , Riccardo Zurla
CPC classification number: G05F3/26
Abstract: A current mirror includes an input transistor and an output transistor, wherein the sources of the input and output transistor are connected to supply voltage node. The gates of the input and output transistor are connected through a switch. A first current source is coupled to the input transistor to provide an input current. A copy transistor has a source connected to the supply node and a gate connected to the gate of the input transistor at a mirror node. A second current source is coupled to the copy transistor to provide a copy current. A source-follower transistor has its source connected to the mirror node and its gate connected to the drain of the copy transistor. Charge sharing at a mirror node occurs in response to actuation of the switch and the source-follower transistor is turned on in response thereto to discharge the mirror node.
-
公开(公告)号：US20170178734A1
公开(公告)日：2017-06-22
申请号：US15244664
申请日：2016-08-23
Inventor： Marco Pasotti , Fabio De Santis , Roberto Bregoli , Dario Livornesi , Sandor Petenyi
IPC: G11C16/30 , G11C5/14 , G11C16/04 , H01L27/115 , G11C16/28
CPC classification number: G11C16/30 , G05F3/30 , G11C5/147 , G11C16/0408 , G11C16/0433 , G11C16/10 , G11C16/28 , G11C2216/10 , H01L27/11521 , H01L27/1156 , H03F3/45188 , H03F3/45475 , H03F2200/456 , H03F2203/45341 , H03F2203/45342 , H03F2203/45528 , H03F2203/45674 , H03F2203/45676
Abstract: A device for generating a reference voltage includes a first non-volatile memory cell provided with a control-gate transistor and a reading transistor. The control-gate transistor includes a gate terminal, a body, a first conduction terminal and a second conduction terminal. The first conduction terminal and the second conduction terminal are connected together to form a control-gate terminal. The reading transistor includes a gate terminal that is connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal. The device also includes a second, equivalent, memory cell. The source terminal of the first non-volatile memory cell and the source terminal of the second equivalent memory cell are connected together.
-
公开(公告)号：US20170178727A1
公开(公告)日：2017-06-22
申请号：US15433795
申请日：2017-02-15
Inventor： Marco Pasotti , Marcella Carissimi , Vikas Rana
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0026 , G11C2013/0078
Abstract: An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes a first decoder circuit having a respective plurality of transistors having a first conductivity type being coupled together and to a given bitline from among the plurality thereof and configured to inject a program current pulse into a selected PCM cell. In addition, the integrated circuit includes a second decoder circuit having a plurality of transistors having a second conductivity type being coupled together and to the given bitline and configured to discharge the given bitline at an end of the program current pulse.
-
-
-
-
-
-
-
-
-
Search Results
59
records
(took 0.035 seconds)
