公开(公告)号：US20170178734A1

公开(公告)日：2017-06-22

申请号：US15244664

申请日：2016-08-23

Applicant: STMicroelectronics S.r.l ,  STMicroelectronics Design & Application S.R.O.

Inventor： Marco Pasotti ,  Fabio De Santis ,  Roberto Bregoli ,  Dario Livornesi ,  Sandor Petenyi

IPC: G11C16/30 ,  G11C5/14 ,  G11C16/04 ,  H01L27/115 ,  G11C16/28

CPC classification number: G11C16/30 ,  G05F3/30 ,  G11C5/147 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/10 ,  H01L27/11521 ,  H01L27/1156 ,  H03F3/45188 ,  H03F3/45475 ,  H03F2200/456 ,  H03F2203/45341 ,  H03F2203/45342 ,  H03F2203/45528 ,  H03F2203/45674 ,  H03F2203/45676

Abstract: A device for generating a reference voltage includes a first non-volatile memory cell provided with a control-gate transistor and a reading transistor. The control-gate transistor includes a gate terminal, a body, a first conduction terminal and a second conduction terminal. The first conduction terminal and the second conduction terminal are connected together to form a control-gate terminal. The reading transistor includes a gate terminal that is connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal. The device also includes a second, equivalent, memory cell. The source terminal of the first non-volatile memory cell and the source terminal of the second equivalent memory cell are connected together.

公开(公告)号：US11863066B2

公开(公告)日：2024-01-02

申请号：US18168936

申请日：2023-02-14

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Vikas Rana ,  Marco Pasotti ,  Fabio De Santis

IPC: H02M3/07 ,  G11C5/14

CPC classification number: H02M3/07 ,  G11C5/145 ,  H02M3/071

Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

公开(公告)号：US11665915B2

公开(公告)日：2023-05-30

申请号：US16863856

申请日：2020-04-30

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Fabio De Santis ,  Vikas Rana

IPC: H01L27/105 ,  H01L27/11521 ,  H01L27/112 ,  G11C29/00 ,  H01L27/11519 ,  H01L27/11558 ,  G11C16/04 ,  H01L21/66

CPC classification number: H01L27/1052 ,  G11C29/006 ,  H01L27/1122 ,  H01L27/1124 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11558 ,  G11C16/0433 ,  H01L22/00

Abstract: According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

公开(公告)号：US11611275B2

公开(公告)日：2023-03-21

申请号：US17866372

申请日：2022-07-15

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Vikas Rana ,  Marco Pasotti ,  Fabio De Santis

IPC: H02M3/07 ,  G11C5/14

Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

公开(公告)号：US09442149B2

公开(公告)日：2016-09-13

申请号：US14326263

申请日：2014-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Marco Pasotti ,  Fabio De Santis

IPC: H01H31/12 ,  G01R31/02 ,  G01R19/165

CPC classification number: G01R31/025 ,  G01R19/16571

Abstract: An embodiment of a measuring circuit for measuring the leakage current flowing in a portion of an electronic device when said portion is biased by a biasing unit of the electronic device is proposed. The measuring circuit includes a first section configured to generate a threshold current, a second section configured to receive the leakage current, a third section configured to compare the threshold current with the leakage current, and a fourth section configured to generate an output voltage based on the comparison between the threshold current and the leakage current. Said first section is configured to set the value of said threshold current to a different value at each reiteration of an operating cycle. Said fourth section is configured to measure said leakage current based on a detection of a change in the value of the output voltage between two reiterations of the operating cycle.

Abstract translation: 提出了一种测量电路的实施例，用于测量当电子设备的偏置单元偏压所述部分时在电子设备的一部分中流动的漏电流。 测量电路包括被配置为产生阈值电流的第一部分，被配置为接收泄漏电流的第二部分，被配置为将阈值电流与漏电流进行比较的第三部分，以及被配置为基于 阈值电流与漏电流的比较。 所述第一部分被配置为在操作周期的每次重复时将所述阈值电流的值设置为不同的值。 所述第四部分被配置为基于在操作周期的两次重复之间的输出电压的值的变化的检测来测量所述泄漏电流。

公开(公告)号：US11424676B2

公开(公告)日：2022-08-23

申请号：US17145107

申请日：2021-01-08

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Vikas Rana ,  Marco Pasotti ,  Fabio De Santis

IPC: H02M3/07 ,  G11C5/14

Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

公开(公告)号：US20210234460A1

公开(公告)日：2021-07-29

申请号：US17145107

申请日：2021-01-08

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Vikas Rana ,  Marco Pasotti ,  Fabio De Santis

IPC: H02M3/07

Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

公开(公告)号：US09634562B1

公开(公告)日：2017-04-25

申请号：US15177830

申请日：2016-06-09

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Vikas Rana ,  Marco Pasotti ,  Fabio De Santis

IPC: G05F1/10 ,  G05F3/02 ,  H02M3/07

CPC classification number: H02M3/073

Abstract: A voltage doubler circuit supports operation in a positive voltage boosting mode to positively boost voltage from a first node to a second node and operation in a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuits receive two clock signals having different high voltage levels. A series of voltage doubler circuit are connected in a charge pump with controllable operation in the first and second modes. A connecting circuit interconnects the first and second nodes of the voltage doubler circuits to provide a first connection path, with a first input voltage, to support the positive voltage boosting mode operation and a second connection path, with a proper input voltage, to support the negative voltage boosting mode. A discharge circuit is provided to discharge the voltage doubler circuits when operation of the charge pump circuit is terminated.

公开(公告)号：US20170047909A1

公开(公告)日：2017-02-16

申请号：US14826017

申请日：2015-08-13

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Vikas Rana ,  Fabio De Santis

IPC: H03K3/012 ,  H03K17/687

CPC classification number: H03K17/102

Abstract: A cascode voltage generating circuit and method are provided. The circuit includes four switching elements. In a high voltage operation mode, the first and second switching elements, respectively, couple a first intermediate voltage input node to a first intermediate voltage output node, and a second intermediate voltage input node to a second intermediate voltage output node. In a low voltage operation mode, the third switching element couples the first and second intermediate voltage input nodes to a ground reference voltage level, and the fourth switching element couples the first and second intermediate voltage output nodes to a supply voltage level.

Abstract translation: 提供了共源共栅电压发生电路和方法。 该电路包括四个开关元件。 在高电压运行模式中，第一和第二开关元件分别将第一中间电压输入节点耦合到第一中间电压输出节点，将第二中间电压输入节点耦合到第二中间电压输出节点。 在低电压操作模式中，第三开关元件将第一和第二中间电压输入节点耦合到接地参考电压电平，第四开关元件将第一和第二中间电压输出节点耦合到电源电压电平。

公开(公告)号：US09443566B2

公开(公告)日：2016-09-13

申请号：US14061977

申请日：2013-10-24

Applicant: STMicroelectronics S.R.L.

Inventor： Marcella Carissimi ,  Marco Pasotti ,  Fabio De Santis

IPC: G11C16/28 ,  G11C7/06 ,  G11C7/08 ,  G11C16/04

CPC classification number: G11C7/22 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/10 ,  G11C16/0441 ,  G11C16/28

Abstract: An embodiment solution for operating a non-volatile memory of a complementary type is proposed. The non-volatile memory includes a plurality of sectors of memory cells, each memory cell being adapted to take a programmed state or an erased state. Moreover, the memory cells are arranged in locations each formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. In an embodiment, a corresponding method includes the following steps: selecting at least one of the sectors, determining an indication of the number of memory cells in the programmed state and an indication of the number of memory cells in the erased state of the selected sector, and identifying the condition of the selected sector according to a comparison between the indication of the number of memory cells in the programmed state and the indication of the number of memory cells in the erased state.

Abstract translation: 提出了用于操作互补型非易失性存储器的实施例解决方案。 非易失性存储器包括存储器单元的多个扇区，每个存储器单元适于采取编程状态或擦除状态。 此外，存储单元被布置在由直接存储单元和互补存储单元形成的位置中。 当相应的存储器单元处于相同的状态并且处于写入状态时，非易失性存储器的每个扇区处于非写入状态，其中当其中的每个位置存储第一逻辑值或第二逻辑值时， 位置分别处于不同状态的第一组合或处于不同状态的第二组合中。 在一个实施例中，相应的方法包括以下步骤：选择扇区中的至少一个，确定编程状态下的存储器单元的数量的指示以及所选扇区的擦除状态中的存储器单元的数量的指示 并且根据编程状态下的存储单元的数量的指示与擦除状态下的存储单元的数量的指示之间的比较来识别所选扇区的状况。