公开(公告)号：US20030113981A1

公开(公告)日：2003-06-19

申请号：US10284031

申请日：2002-10-29

Applicant: STMicroelectronics S.r.I.

Inventor： Chantal Combi ,  Matteo Fiorito ,  Marta Mottura ,  Giuseppe Visalli ,  Benedetto Vigna

IPC: H01L021/00 ,  H01L021/76

CPC classification number: H01L21/764 ,  H01L21/76208 ,  H01L21/76229 ,  H01L27/08

Abstract: A process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling are disclosed. The method includes providing a wafer of semiconductor material having a substrate; forming a plurality of first mutually adjacent trenches, open on a first face of the wafer, which have a depth and a width and define walls); by thermal oxidation, completely oxidizing the walls and filling at least partially the first trenches, so as to form an insulating structure of dielectric material; and removing one portion of the substrate comprised between the insulating structure and a second face of the wafer, opposite to the first face of the wafer.

Abstract translation: 公开了一种用于制造集成电子器件的半导体晶片和用于电磁去耦的结构的工艺。 该方法包括提供具有基板的半导体材料晶片; 形成多个第一相互相邻的沟槽，在晶片的第一面上开口，其具有深度和宽度并限定壁）; 通过热氧化，完全氧化壁并至少部分地填充第一沟槽，以形成介电材料的绝缘结构; 以及移除所述绝缘结构和所述晶片的与所述晶片的第一面相对的第二面之间的衬底的一部分。

公开(公告)号：US20030109183A1

公开(公告)日：2003-06-12

申请号：US10243972

申请日：2002-09-12

Applicant: STMicroelectronics S.r.I. ,  Hewlett-Packard Company

Inventor： Ubaldo Mastromatteo ,  Mauro Bombonati ,  Daniela Morin ,  Marta Mottura ,  Mauro Marchi

IPC: H01R009/22

CPC classification number: B81C1/00269 ,  H01L21/185 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13164 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/812 ,  H01L2224/81201 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/013

Abstract: A process for bonding two distinct substrates that integrate microsystems, including the steps of forming micro-integrated devices in at least one of two substrates using micro-electronic processing techniques and bonding the substrates. Bonding is performed by forming on a first substrate bonding regions of deformable material and pressing the substrates one against another so as to deform the bonding regions and to cause them to react chemically with the second substrate. The bonding regions are preferably formed by a thick layer of a material chosen from among aluminum, copper and nickel, covered by a thin layer of a material chosen from between palladium and platinum. Spacing regions ensure exact spacing between the two wafers.

公开(公告)号：US20020127761A1

公开(公告)日：2002-09-12

申请号：US10037484

申请日：2001-12-19

Applicant: STMicroelectronics S.r.I.

Inventor： Marta Mottura ,  Alessandra Fischetti ,  Marco Ferrera ,  Bernardino Zerbini ,  Mauro Bombonati

IPC: H01L021/00

CPC classification number: H01L21/2007 ,  H01L21/76256

Abstract: A process for manufacturing components in a multi-layer wafer, including the steps of: providing a multi-layer wafer comprising a first semiconductor material layer, a second semiconductor material layer (, and a dielectric material layer arranged between the first and the second semiconductor material layer; and removing the first semiconductor material layer initially by mechanically thinning the first semiconductor material layer, so as to form a residual conductive layer, and subsequently by chemically removing the residual conductive layer. In one application, the multi-layer wafer is bonded to a first wafer of semiconductor material, with the second semiconductor material layer facing the first wafer, after micro-electromechanical structures have been formed in the second semiconductor material layer of the multi-layer wafer.

Abstract translation: 一种用于制造多层晶片中的部件的方法，包括以下步骤：提供包括第一半导体材料层，第二半导体材料层（以及布置在第一和第二半导体之间的介电材料层）的多层晶片 最初通过机械稀化第一半导体材料层去除第一半导体材料层，从而形成残留的导电层，随后通过化学去除残留的导电层，在一个应用中，多层晶片被粘合 在多层晶片的第二半导体材料层中形成微机电结构之后，将第二半导体材料层面向第一晶片的半导体材料的第一晶片。