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公开(公告)号：US06401224B1
公开(公告)日：2002-06-04
申请号：US09261100
申请日：1999-03-02
IPC分类号： G01R3128
CPC分类号： G01R31/3185
摘要： A test method suitable for testing at least one integrated circuit which, on a main area, has contact areas that serve to transfer signals during a first operating mode of the circuit. Only some of the contact areas are contact-connected to test contacts of a test apparatus and the circuit is put into a second operating mode in which the signals which are transferred via at least one of the non-contact-connected contact areas in the first operating mode are transferred via at least one of the contact-connected contact areas.
摘要翻译： 一种适用于测试至少一个集成电路的测试方法，该集成电路在主区域具有用于在电路的第一操作模式期间传送信号的接触区域。 只有一些接触区域接触连接到测试装置的测试触点，并且电路进入第二操作模式，其中通过第一操作模式中的至少一个非接触连接的接触区域传送的信号 操作模式通过至少一个接触连接的接触区域传送。
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公开(公告)号：US06480024B2
公开(公告)日：2002-11-12
申请号：US10046395
申请日：2001-10-19
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Michael Markert , Thilo Marx , Torsten Partsch , Sabine Schöniger Kieser , Peter Schrögmeier , Michael Sommer , Christian Weis
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Michael Markert , Thilo Marx , Torsten Partsch , Sabine Schöniger Kieser , Peter Schrögmeier , Michael Sommer , Christian Weis
IPC分类号： H03K190173
CPC分类号： H03K5/133 , H03K2005/00065 , H03K2005/00071 , H03K2005/00091
摘要： A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path sections can be connected to an output terminal via a multiplexer. A selection circuit includes two signal path sections which are connected between supply voltage potentials. The selection circuit has two complimentary transistors which are connected in series and has source-end programmable elements. These transistors can be driven by complimentary control signals. This permits the delay to be programmed flexibly with little expenditure on circuitry.
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3.发明授权Integrated memory having column decoder for addressing corresponding bit line 失效具有用于寻址相应位线的列解码器的集成存储器公开(公告)号：US06188642B1
公开(公告)日：2001-02-13
申请号：US09348736
申请日：1999-07-06
IPC分类号： G11C800
CPC分类号： G11C8/00
摘要： The integrated memory has a column decoder for decoding column addresses and for addressing corresponding bit lines. The memory also has a first column address bus, which is used to transfer first column addresses to the column decoder, and a second column address bus, which is used to transfer second column addresses to the column decoder. The column decoder in each case addresses bit lines which correspond to the first and second column addresses supplied to it.
摘要翻译： 集成存储器具有用于解码列地址并用于寻址对应位线的列解码器。 存储器还具有第一列地址总线，其用于将第一列地址传送到列解码器，以及第二列地址总线，其用于将第二列地址传送到列解码器。 列解码器在每种情况下都对应于提供给它的第一列地址和第二列地址的位线。
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4.发明授权Method and circuit configuration for read-write mode control of a synchronous memory 有权用于同步存储器的读写模式控制的方法和电路配置公开(公告)号：US06359832B2
公开(公告)日：2002-03-19
申请号：US09773222
申请日：2001-01-31
IPC分类号： G11C800
CPC分类号： G11C7/1072 , G11C7/12 , G11C11/4094
摘要： A read-write mode control method is described in which a waiting time during a reading process can be shortened by conducting a read instruction with auto-precharging in a first circuit part. The first circuit part is separate from a second circuit part used for conducting the write instruction, since a memory controller does not need to insert any wait cycles between a write instruction and an associated activate signal.
摘要翻译： 描述了一种读写模式控制方法，其中可以通过在第一电路部分中进行具有自动预充电的读取指令来缩短读取处理期间的等待时间。 第一电路部分与用于执行写指令的第二电路部分分开，因为存储器控制器不需要在写指令和相关联的激活信号之间插入任何等待周期。
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5.发明授权Integrated memory with row access control to activate and precharge row lines, and method of operating such a memory 有权具有行访问控制的集成存储器，用于激活和预充行行，以及操作这种存储器的方法公开(公告)号：US06396755B2
公开(公告)日：2002-05-28
申请号：US09864978
申请日：2001-05-24
IPC分类号： G11C700
CPC分类号： G11C8/00
摘要： An integrated memory has memory cells which are each connected to a row line to select one of the memory cells and to a column line to read or write a data signal. A row access controller is used to activate one of the row lines to select one of the memory cells and to control a precharging operation to precharge one of the row lines. A precharge command initiates a precharging operation. The precharging operation for an activated row line is triggered by the row access controller when the reading or writing of a data signal has been finished and when a defined time interval, during which the row line must at least be activated, has elapsed since the activation. As a result, a precharging operation of the activated row line is controlled in a self-adjusting manner. A method of operating an integrated memory is also provided.
摘要翻译： 集成存储器具有各自连接到行线的存储单元，以选择存储器单元之一和列线来读取或写入数据信号。 行访问控制器用于激活行行之一以选择存储器单元之一并且控制预充电操作以对行行之一进行预充电。 预充电命令启动预充电操作。 激活的行线的预充电操作在数据信号的读取或写入已经完成时由行存取控制器触发，并且当激活行至少必须被激活的定义的时间间隔已经过去时 。 结果，以自动调节的方式控制激活的行线的预充电操作。 还提供了一种操作集成存储器的方法。
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公开(公告)号：US06404699B1
公开(公告)日：2002-06-11
申请号：US09603742
申请日：2000-06-26
IPC分类号： G11C800
CPC分类号： G11C7/22 , G11C7/1045 , G11C11/4076
摘要： The integrated circuit has an activation decoder whose outputs are connected to the inputs of a command decoder. When an activation signal is at a first logic level, the activation decoder produces at its outputs a command supplied to it from command inputs. When the activation signal is at a second logic level, the activation decoder produces a deactivation command at its outputs irrespective of the command supplied to it from the command inputs. The command decoder does not activate any of its outputs when the deactivation command is being supplied to its inputs. The command decoder activates one of its outputs in each case when a different command is supplied to its inputs.
摘要翻译： 集成电路具有激活解码器，其输出端连接到命令解码器的输入端。 当激活信号处于第一逻辑电平时，激活解码器在其输出端产生从命令输入提供给它的命令。 当激活信号处于第二逻辑电平时，激活解码器在其输出处产生停用命令，而与从命令输入提供给其的命令无关。 当向其输入提供停用命令时，命令解码器不会激活其任何输出。 当向其输入提供不同的命令时，命令解码器在每种情况下激活其一个输出。
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7.发明授权Integrated memory with a block writing function and global amplifiers requiring less space 有权具有块写入功能的集成存储器和需要较少空间的全局放大器公开(公告)号：US06351419B1
公开(公告)日：2002-02-26
申请号：US09580986
申请日：2000-05-30
IPC分类号： G11C700
摘要： An integrated memory has a first operating mode, in which, during each write access, only one of the two global amplifiers is active and transmits a datum via one of the local amplifiers to the corresponding bit line. Moreover, the memory has a second operating mode, in which, during each write access, both global amplifiers are simultaneously active and transmit a common datum via in each case at least one of the local amplifiers to the corresponding bit lines.
摘要翻译： 集成存储器具有第一操作模式，其中在每个写入期间，两个全局放大器中只有一个是有源的，并且通过一个本地放大器将数据发送到对应的位线。 此外，存储器具有第二操作模式，其中在每个写入期间，两个全局放大器同时被激活，并且在每个情况下将至少一个本地放大器的公共数据通路传送到对应的位线。
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公开(公告)号：US06437410B1
公开(公告)日：2002-08-20
申请号：US09603749
申请日：2000-06-26
申请人： Stefan Dietrich , Musa Saglam , Peter Schrögmeier , Michael Markert , Sabine Schöniger , Christian Weis
发明人： Stefan Dietrich , Musa Saglam , Peter Schrögmeier , Michael Markert , Sabine Schöniger , Christian Weis
IPC分类号： H01L2976
CPC分类号： G11C7/1066 , G11C8/00 , G11C8/10
摘要： The integrated memory has a first address path, via which the address terminals are connected to first selection lines of a first group and which has corresponding first lines and a first decoder circuit. In addition, the integrated memory has a second address path, via which the address terminals are connected to first selection lines of a second group and which has corresponding second lines and a second decoder circuit. The first decoder circuit is faster than the second decoder circuit. The first lines have a longer signal propagation time than the second lines.
摘要翻译： 集成存储器具有第一地址路径，通过该第一地址路径，地址端子连接到第一组的第一选择线并且具有对应的第一行和第一解码器电路。 此外，集成存储器具有第二地址路径，通过该第二地址路径，地址端子连接到第二组的第一选择线并具有对应的第二线和第二解码器电路。 第一解码器电路比第二解码器电路快。 第一行具有比第二行更长的信号传播时间。
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9.发明授权Integrated circuit having a decoder unit and an additional input of a decoder unit to determine a number of outputs to be activated 有权集成电路具有解码器单元和解码器单元的附加输入，以确定要激活的输出的数量公开(公告)号：US06385123B1
公开(公告)日：2002-05-07
申请号：US09606589
申请日：2000-06-29
IPC分类号： G11C800
CPC分类号： G11C8/10
摘要： The integrated circuit has a first decoder unit and a second decoder unit D2 connected in parallel with the latter, which decode the input signals fed to them in a different way in each case. The inputs of the second decoder unit D2 are connected to a respective one of the inputs of the first decoder unit D1. n lines L1 to be selected are each connected to a respective one of the outputs of the two decoder units D1, D2. Via their outputs, the first decoder unit D1 and the second decoder unit D2 determine, in a first operating mode and in a second operating mode, respectively, the potentials of the lines L1 to be selected.
摘要翻译： 集成电路具有第一解码器单元和与其并联连接的第二解码器单元D2，其在每种情况下以不同的方式解码馈送给它们的输入信号。 第二解码器单元D2的输入连接到第一解码器单元D1的相应输入端。 要选择的n行L1各自连接到两个解码器单元D1，D2的输出中的相应一个。 通过其输出，第一解码器单元D1和第二解码器单元D2分别在第一操作模式和第二操作模式中确定要选择的线L1的电位。
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公开(公告)号：US06310824B1
公开(公告)日：2001-10-30
申请号：US09662255
申请日：2000-09-14
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1018
摘要： The memory has a bidirectional address counting unit C1; S, which performs a counting operation for the purpose of generating internal column addresses from an external column address A7 . . . 0. In this case, the counting direction is dependent on the burst operating mode and on an address bit A1 of the external column address. Moreover, the memory has a transformation unit C2; SR2, which forwards partial addresses A2 . . . 1′; PA3 . . . 0′ generated by the address counting unit C1; S either unchanged or incremented by the value 1 to the second column decoder CDEC2, in a manner dependent on the burst operating mode and a further address bit A0 of the external column address A7 . . . 0.
摘要翻译： 存储器具有双向地址计数单元C1; S，其执行用于从外部列地址A7生成内部列地址的计数操作。 。 。 在这种情况下，计数方向取决于突发运行模式和外部列地址的地址位A1。 此外，存储器具有变换单元C2; SR2转发部分地址A2。 。 。 1'; PA3。 。 。 0'由地址计数单元C1产生; S以取决于突发操作模式的方式和外部列地址A7的另一地址位A0以不变或递增值1到第二列解码器CDEC2。 。 。 0。
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