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    Floating gate avalanche injection MOS transistors with high K dielectric control gates
    3.
    发明授权
    Floating gate avalanche injection MOS transistors with high K dielectric control gates 失效
    浮动栅极雪崩注入MOS晶体管，具有高K介质控制栅极

    公开(公告)号：US6008091A

    公开(公告)日：1999-12-28

    申请号：US14030

    申请日：1998-01-27

    申请人： Richard William Gregor ,  Isik C. Kizilyalli ,  Pradip Kumar Roy

    发明人： Richard William Gregor ,  Isik C. Kizilyalli ,  Pradip Kumar Roy

    IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L29/511 ,  H01L21/28273

    摘要： The specification describes intergate dielectrics between the floating silicon gate and the control silicon gate in MOS memory devices. The intergate dielectrics are composite structures of SiO.sub.2 --Ta.sub.2 O.sub.5 --SiO.sub.2 with the first SiO.sub.2 layer grown on the floating gate,, and all layers preferably produced in situ in an LPCVD reactor. After formation of the composite SiO.sub.2 --Ta.sub.2 O.sub.5 --SiO.sub.2 dielectric, it is annealed at low pressure to densify the SiO.sub.2 layers. Electrical measurements show that the charge trap density in the intergate dielectric is substantially lower than in layered dielectrics produced by prior techniques.

    摘要翻译： 本说明书描述了MOS存储器件中的浮置硅栅极和控制硅栅极之间的栅极电介质。 隔间电介质是SiO 2 -Ta 2 O 5 -SiO 2与在浮栅上生长的第一SiO 2层的复合结构，并且所有层优选在LPCVD反应器中原位制备。 在形成复合SiO 2 -Ta 2 O 5 -SiO 2电介质后，在低压下进行退火以使SiO 2层致密化。 电测量显示，间隔电介质中的电荷陷阱密度基本上低于由现有技术产生的分层电介质。

    Method of reducing dielectric damage from plasma etch charging
    4.
    发明授权
    Method of reducing dielectric damage from plasma etch charging 失效
    减少等离子体蚀刻充电的电介质损伤的方法

    公开(公告)号：US5843827A

    公开(公告)日：1998-12-01

    申请号：US724128

    申请日：1996-09-30

    申请人： Richard William Gregor ,  Chung Wai Leung

    发明人： Richard William Gregor ,  Chung Wai Leung

    IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L21/28026

    摘要： A method of suppressing damage to gate dielectrics by reducing the electrical field across the gate dielectric during plasma etching, photoresist stripping, or plasma assisted deposition of the overlying conductor to be etched. Openings in the gate oxide in the vicinity of the gates to be formed place the two conductive layers in contact with each other before the gates are formed and allows for the underlying conductive layer (usually the substrate) to be exposed to the plasma as the overlying unmasked conductive layer (usually polysilicon) is etched away. Preferably, the layer to be etched is deposited to be in contact with the underlying layer at the openings. This technique is applicable to integrated capacitor structures and other susceptible structures with a dielectric layer between two conductors.

    摘要翻译： 通过在等离子体蚀刻，光致抗蚀剂剥离或待蚀刻的上覆导体的等离子体辅助沉积期间减小栅极电介质两端的电场来抑制对栅极电介质的损伤的方法。 要形成的栅极附近的栅极氧化物中的开口使得两个导电层在栅极形成之前彼此接触，并且允许下面的导电层（通常是衬底）暴露于等离子体作为覆盖 未掩蔽的导电层（通常是多晶硅）被蚀刻掉。 优选地，被蚀刻的层被沉积成与开口处的下层接触。 该技术适用于在两个导体之间具有介电层的集成电容器结构和其他敏感结构。