公开(公告)号：US06847077B2

公开(公告)日：2005-01-25

申请号：US10180910

申请日：2002-06-25

申请人： Sylvia W. Thomas ,  Michael Jay Parrish ,  Tony G. Ivanov ,  Edward Belden Harris ,  Richard William Gregor ,  Michael Scott Carroll

发明人： Sylvia W. Thomas ,  Michael Jay Parrish ,  Tony G. Ivanov ,  Edward Belden Harris ,  Richard William Gregor ,  Michael Scott Carroll

IPC分类号： H01L21/3205 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/532 ,  H01L27/04 ,  H01L27/108

CPC分类号： H01L28/40 ,  H01L21/76838 ,  H01L23/5223 ,  H01L23/53228 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a capacitor integrated in a damascene structure. In one embodiment, the capacitor is formed entirely within a metallization layer of a damascene structure, having therein a semiconductor device component. Preferably, the capacitor is formed within a trench, having been etched in the dielectric material of the metal layer and the capacitor includes a first capacitor electrode formed within the recess in electrical contact with the device component of the metallization layer. An insulator may be formed over the first capacitor electrode, with a second capacitor electrode formed over the insulator. These elements are preferably conformally deposited within the trench, thereby forming a recess, a portion of which extends within the trench. A subsequently fabricated device component may then be placed in electrical contact with the second capacitor electrode.

摘要翻译： 具有集成在镶嵌结构中的电容器的半导体器件。 在一个实施例中，电容器完全形成在其中具有半导体器件部件的镶嵌结构的金属化层内。 优选地，电容器形成在已经在金属层的介电材料中蚀刻的沟槽内，并且电容器包括形成在凹部内的与金属化层的器件部件电接触的第一电容器电极。 可以在第一电容器电极上形成绝缘体，在绝缘体上形成第二电容器电极。 这些元件优选地在沟槽内共形沉积，从而形成凹槽，其中一部分在沟槽内延伸。 然后可以将随后制造的器件部件放置成与第二电容器电极电接触。

公开(公告)号：US5843827A

公开(公告)日：1998-12-01

申请号：US724128

申请日：1996-09-30

申请人： Richard William Gregor ,  Chung Wai Leung

发明人： Richard William Gregor ,  Chung Wai Leung

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L21/28026

摘要： A method of suppressing damage to gate dielectrics by reducing the electrical field across the gate dielectric during plasma etching, photoresist stripping, or plasma assisted deposition of the overlying conductor to be etched. Openings in the gate oxide in the vicinity of the gates to be formed place the two conductive layers in contact with each other before the gates are formed and allows for the underlying conductive layer (usually the substrate) to be exposed to the plasma as the overlying unmasked conductive layer (usually polysilicon) is etched away. Preferably, the layer to be etched is deposited to be in contact with the underlying layer at the openings. This technique is applicable to integrated capacitor structures and other susceptible structures with a dielectric layer between two conductors.

摘要翻译： 通过在等离子体蚀刻，光致抗蚀剂剥离或待蚀刻的上覆导体的等离子体辅助沉积期间减小栅极电介质两端的电场来抑制对栅极电介质的损伤的方法。 要形成的栅极附近的栅极氧化物中的开口使得两个导电层在栅极形成之前彼此接触，并且允许下面的导电层（通常是衬底）暴露于等离子体作为覆盖 未掩蔽的导电层（通常是多晶硅）被蚀刻掉。 优选地，被蚀刻的层被沉积成与开口处的下层接触。 该技术适用于在两个导体之间具有介电层的集成电容器结构和其他敏感结构。

公开(公告)号：US07151059B2

公开(公告)日：2006-12-19

申请号：US10762788

申请日：2004-01-22

申请人： Samir Chaudhry ,  Sidhartha Sen ,  Sundar Srinivasan Chetlur ,  Richard William Gregor ,  Pradip Kumar Roy

发明人： Samir Chaudhry ,  Sidhartha Sen ,  Sundar Srinivasan Chetlur ,  Richard William Gregor ,  Pradip Kumar Roy

IPC分类号： H01L21/31

CPC分类号： H01L21/28194 ,  C30B29/06 ,  C30B33/005 ,  H01L21/02238 ,  H01L21/26586 ,  H01L21/28167 ,  H01L21/28273 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/31662 ,  H01L21/3185 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/513 ,  H01L29/517

摘要： A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 μm or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.

摘要翻译： 公开了减小的特征尺寸MOS晶体管及其制造方法。 本发明减少短信道效应，但不包括LDD结构。在说明性实施例中，MOS晶体管的栅极长度为1.25μm或更小。 示例性MOS晶体管包括与衬底形成平面且基本上无应力的界面的栅极氧化物。 由于氧化物/衬底界面的平坦性和基本无应力的性质，热载流子的发生率以及有害的热载流子效应降低。 通过消除LDD结构的使用，制造复杂度降低，串联源极 - 漏极电阻降低，从而提高驱动电流和开关速度。

公开(公告)号：US06740912B1

公开(公告)日：2004-05-25

申请号：US09597012

申请日：2000-06-20

申请人： Samir Chaudhry ,  Sidharta Sen ,  Sundar Srinivasan Chetlur ,  Richard William Gregor ,  Pradip Kumar Roy

发明人： Samir Chaudhry ,  Sidharta Sen ,  Sundar Srinivasan Chetlur ,  Richard William Gregor ,  Pradip Kumar Roy

IPC分类号： H01L2976

CPC分类号： H01L21/28194 ,  C30B29/06 ,  C30B33/005 ,  H01L21/02238 ,  H01L21/26586 ,  H01L21/28167 ,  H01L21/28273 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/31662 ,  H01L21/3185 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/513 ,  H01L29/517

摘要： A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 &mgr;m or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.

摘要翻译： 公开了减小的特征尺寸MOS晶体管及其制造方法。 本发明减少短信道效应，但不包括LDD结构。在说明性实施例中，MOS晶体管的栅极长度为1.25μm或更小。 示例性MOS晶体管包括与衬底形成平面且基本上无应力的界面的栅极氧化物。 由于氧化物/衬底界面的平坦性和基本无应力的性质，热载流子的发生率以及有害的热载流子效应降低。 通过消除LDD结构的使用，制造复杂度降低，串联源极 - 漏极电阻降低，从而提高驱动电流和开关速度。

公开(公告)号：US6008091A

公开(公告)日：1999-12-28

申请号：US14030

申请日：1998-01-27

申请人： Richard William Gregor ,  Isik C. Kizilyalli ,  Pradip Kumar Roy

发明人： Richard William Gregor ,  Isik C. Kizilyalli ,  Pradip Kumar Roy

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/511 ,  H01L21/28273

摘要： The specification describes intergate dielectrics between the floating silicon gate and the control silicon gate in MOS memory devices. The intergate dielectrics are composite structures of SiO.sub.2 --Ta.sub.2 O.sub.5 --SiO.sub.2 with the first SiO.sub.2 layer grown on the floating gate,, and all layers preferably produced in situ in an LPCVD reactor. After formation of the composite SiO.sub.2 --Ta.sub.2 O.sub.5 --SiO.sub.2 dielectric, it is annealed at low pressure to densify the SiO.sub.2 layers. Electrical measurements show that the charge trap density in the intergate dielectric is substantially lower than in layered dielectrics produced by prior techniques.

摘要翻译： 本说明书描述了MOS存储器件中的浮置硅栅极和控制硅栅极之间的栅极电介质。 隔间电介质是SiO 2 -Ta 2 O 5 -SiO 2与在浮栅上生长的第一SiO 2层的复合结构，并且所有层优选在LPCVD反应器中原位制备。 在形成复合SiO 2 -Ta 2 O 5 -SiO 2电介质后，在低压下进行退火以使SiO 2层致密化。 电测量显示，间隔电介质中的电荷陷阱密度基本上低于由现有技术产生的分层电介质。