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1.发明授权公开(公告)号：US06847077B2
公开(公告)日：2005-01-25
申请号：US10180910
申请日：2002-06-25
申请人： Sylvia W. Thomas , Michael Jay Parrish , Tony G. Ivanov , Edward Belden Harris , Richard William Gregor , Michael Scott Carroll
发明人： Sylvia W. Thomas , Michael Jay Parrish , Tony G. Ivanov , Edward Belden Harris , Richard William Gregor , Michael Scott Carroll
IPC分类号： H01L21/3205 , H01L21/02 , H01L21/768 , H01L21/822 , H01L23/522 , H01L23/532 , H01L27/04 , H01L27/108
CPC分类号： H01L28/40 , H01L21/76838 , H01L23/5223 , H01L23/53228 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a capacitor integrated in a damascene structure. In one embodiment, the capacitor is formed entirely within a metallization layer of a damascene structure, having therein a semiconductor device component. Preferably, the capacitor is formed within a trench, having been etched in the dielectric material of the metal layer and the capacitor includes a first capacitor electrode formed within the recess in electrical contact with the device component of the metallization layer. An insulator may be formed over the first capacitor electrode, with a second capacitor electrode formed over the insulator. These elements are preferably conformally deposited within the trench, thereby forming a recess, a portion of which extends within the trench. A subsequently fabricated device component may then be placed in electrical contact with the second capacitor electrode.
摘要翻译： 具有集成在镶嵌结构中的电容器的半导体器件。 在一个实施例中，电容器完全形成在其中具有半导体器件部件的镶嵌结构的金属化层内。 优选地，电容器形成在已经在金属层的介电材料中蚀刻的沟槽内，并且电容器包括形成在凹部内的与金属化层的器件部件电接触的第一电容器电极。 可以在第一电容器电极上形成绝缘体，在绝缘体上形成第二电容器电极。 这些元件优选地在沟槽内共形沉积，从而形成凹槽，其中一部分在沟槽内延伸。 然后可以将随后制造的器件部件放置成与第二电容器电极电接触。
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公开(公告)号：US06356496B1
公开(公告)日：2002-03-12
申请号：US09612052
申请日：2000-07-07
IPC分类号： G11C700
CPC分类号： G11C17/16 , G11C11/5692 , G11C17/165
摘要： A resistor fuse for use in a semiconductor device having an operating voltage. In one embodiment, the resistor fuse includes a silicon layer located over a semiconductor wafer and a metal silicide layer located over the silicon layer. The resistor fuse has a predetermined current threshold and is configured to open if a current through the resistor fuse at the operating voltage exceeds the current threshold.
摘要翻译： 一种用于具有工作电压的半导体器件中的电阻器熔丝。 在一个实施例中，电阻器熔丝包括位于半导体晶片之上的硅层和位于硅层之上的金属硅化物层。 电阻器熔丝具有预定的电流阈值，并且如果在工作电压下通过电阻器熔丝的电流超过电流阈值，则该电阻熔断器被配置为打开。
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公开(公告)号：US06194739B1
公开(公告)日：2001-02-27
申请号：US09448521
申请日：1999-11-23
IPC分类号： H01L2358
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A wafer configured for in-process testing of electrical components has a plurality of dies disposed on the wafer, wherein adjacent dies are separated from one another by streets. An in-line device monitor having a first port, a second port, and a device-under-test substantially in line with one another is placed within a street, where the device-under-test is between the first and second ports and is electrically coupled to the first and second ports. With such an arrangement, streets having a width of 100 microns and less are suitable for accomodating a RF-device monitor having ground-signal or ground-signal-ground configurations. As a result, accurate GS or GSG RF-device monitors can be provided in narrow streets of wafers, thereby increasing the amount of wafer area available for circuitry.
摘要翻译： 配置用于电气部件的在线测试的晶片具有设置在晶片上的多个管芯，其中相邻的管芯通过街道彼此分开。 具有第一端口，第二端口和基本上彼此匹配的被测器件的在线设备监视器被放置在街道内，其中被测器件在第一和第二端口之间，并且是 电耦合到第一和第二端口。 通过这样的布置，具有100微米或更小的宽度的街道适合于容纳具有接地信号或地面信号 - 地面配置的RF设备监视器。 因此，可以在晶圆的狭窄街道中提供准确的GS或GSG RF器件监视器，从而增加可用于电路的晶片面积的数量。
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4.发明授权公开(公告)号：US08143120B2
公开(公告)日：2012-03-27
申请号：US13026528
申请日：2011-02-14
IPC分类号： H01L21/8249
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L27/0928 , H01L29/0821
摘要： A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed.
摘要翻译： 一种用于形成在半导体衬底上具有多个不同集电极掺杂密度的双极结型晶体管的工艺，以及包括具有多个不同集电极掺杂密度的双极结型晶体管的集成电路。 第一组晶体管在形成三阱期间形成，用于为也形成在半导体衬底上的互补金属氧化物半导体场效应晶体管提供三阱隔离。 在形成用于场效应晶体管的栅叠层之后的第二掺杂步骤期间，形成具有不同集电极掺杂密度的附加双极结型晶体管。 通过双极晶体管发射极窗口进行的种植体掺杂形成了与先前形成的双极晶体管不同的掺杂密度的双极晶体管。 根据本发明的一个实施例，形成具有六种不同集电极掺杂剂密度（并因此具有六种不同击穿特性）的双极结型晶体管。
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5.发明授权公开(公告)号：US06194750B1
公开(公告)日：2001-02-27
申请号：US09243377
申请日：1999-02-01
IPC分类号： H01L2980
CPC分类号： H01L23/66 , H01L2223/6622 , H01L2223/6627 , H01L2924/0002 , H01L2924/1903 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit is disclosed that comprises structures that confine, shield and/or manipulate the electric fields generated within the integrated circuit so as to improve the performance of the integrated circuit. Such structures include, but are not limited to, transmission lines, capacitors, inductors, filters, and couplers. Although embodiments of the present invention are advantageous for use on many integrated circuits, they are particularly well suited for use with integrated circuits that are disposed on conductive substrates and that operate at high frequencies. An illustrative embodiment of the present invention comprises: an integrated circuit comprising: a first lead and a second lead that are made from a first conductive layer; a substrate; a first plate and a second plate that are made from a second conductive layer; wherein said first plate is sandwiched between and electrically insulated from said first lead and said substrate, said second plate is sandwiched between and electrically insulated from said second lead and said substrate, and said first plate and said second plate are electrically connected.
摘要翻译： 公开了一种集成电路，其包括限制，屏蔽和/或操纵集成电路内产生的电场的结构，以便提高集成电路的性能。 这种结构包括但不限于传输线，电容器，电感器，滤波器和耦合器。 虽然本发明的实施例有利于在许多集成电路上使用，但是它们特别适用于设置在导电基板上并且在高频下工作的集成电路。本发明的说明性实施例包括：集成电路 包括：由第一导电层制成的第一引线和第二引线; 底物; 由第二导电层制成的第一板和第二板; 其中所述第一板被夹在所述第一引线和所述衬底之间并与所述第一引线和所述衬底电绝缘，所述第二板夹在所述第二引线和所述衬底之间并与所述第二引线和所述衬底电绝缘，并且所述第一板和所述第二板电连接。
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6.发明授权公开(公告)号：US07910425B2
公开(公告)日：2011-03-22
申请号：US12727304
申请日：2010-03-19
IPC分类号： H01L21/8249
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L27/0928 , H01L29/0821
摘要： A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed.
摘要翻译： 一种用于形成在半导体衬底上具有多个不同集电极掺杂密度的双极结型晶体管的工艺，以及包括具有多个不同集电极掺杂密度的双极结型晶体管的集成电路。 第一组晶体管在形成三阱期间形成，用于为也形成在半导体衬底上的互补金属氧化物半导体场效应晶体管提供三阱隔离。 在形成用于场效应晶体管的栅叠层之后的第二掺杂步骤期间，形成具有不同集电极掺杂密度的附加双极结型晶体管。 通过双极晶体管发射极窗口进行的种植体掺杂形成了与先前形成的双极晶体管不同的掺杂密度的双极晶体管。 根据本发明的一个实施例，形成具有六种不同集电极掺杂剂密度（并因此具有六种不同击穿特性）的双极结型晶体管。
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7.发明授权公开(公告)号：US07713811B2
公开(公告)日：2010-05-11
申请号：US12243137
申请日：2008-10-01
IPC分类号： H01L21/8249
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L27/0928 , H01L29/0821
摘要： A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed.
摘要翻译： 一种用于形成在半导体衬底上具有多个不同集电极掺杂密度的双极结型晶体管的工艺，以及包括具有多个不同集电极掺杂密度的双极结型晶体管的集成电路。 第一组晶体管在形成三阱期间形成，用于为也形成在半导体衬底上的互补金属氧化物半导体场效应晶体管提供三阱隔离。 在形成用于场效应晶体管的栅叠层之后的第二掺杂步骤期间，形成具有不同集电极掺杂密度的附加双极结型晶体管。 通过双极晶体管发射极窗口进行的种植体掺杂形成了与先前形成的双极晶体管不同的掺杂密度的双极晶体管。 根据本发明的一个实施例，形成具有六种不同集电极掺杂剂密度（并因此具有六种不同击穿特性）的双极结型晶体管。
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8.发明授权公开(公告)号：US06940151B2
公开(公告)日：2005-09-06
申请号：US10261463
申请日：2002-09-30
申请人： Michael Scott Carroll , Yi Ma , Minesh Amrat Patel , Peyman Sana
发明人： Michael Scott Carroll , Yi Ma , Minesh Amrat Patel , Peyman Sana
IPC分类号： H01L21/331 , H01L21/28 , H01L21/318 , H01L21/324 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/8244 , H01L21/8249 , H01L27/06 , H01L27/088 , H01L27/11 , H01L29/51 , H01L29/732 , H01L29/737 , H01L29/78 , H01L31/0392
CPC分类号： H01L29/518 , H01L21/324 , H01L21/823864 , H01L21/8249 , H01L29/6656 , H01L29/6659
摘要： A low-thermal budget, silicon-rich silicon nitride film may include a concentration of hydrogen in Si—H bonds being at least 1.5 times as great as a concentration of hydrogen in N—H bonds. The silicon nitride film suppresses boron diffusion in boron-doped devices when such devices are processed using high-temperature processing operations that conventionally urge boron diffusion. The low-thermal budget, silicon-rich silicon nitride film may be used to form spacers in CMOS devices, it may be used as part of a dielectric stack to prevent shorting in tightly packed SRAM arrays, and it may be used in BiCMOS processing to form a base nitride layer and/or nitride spacers isolating the base from the emitter. Furthermore the low-thermal budget, silicon-rich silicon nitride film may remain covering the CMOS structure while bipolar devices are being formed, as it suppresses the boron diffusion that results in boron penetration and boron-doped poly depletion.
摘要翻译： 低热预算，富含硅的氮化硅膜可能包括Si-H键中的氢浓度至少为N-H键中氢的浓度的1.5倍。 当使用通常促进硼扩散的高温处理操作来处理这种器件时，氮化硅膜抑制硼掺杂器件中的硼扩散。 低热量预算，富含硅的氮化硅膜可用于在CMOS器件中形成间隔物，其可用作电介质堆叠的一部分，以防止紧密堆积的SRAM阵列中的短路，并且可用于BiCMOS处理 形成将基极与发射极隔离的基底氮化物层和/或氮化物间隔物。 此外，低热量预算，富硅的氮化硅膜可能保持覆盖CMOS结构，同时双极器件正在形成，因为它抑制了硼扩散，导致硼渗透和硼掺杂的多晶硅耗尽。
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9.发明申请公开(公告)号：US20100173459A1
公开(公告)日：2010-07-08
申请号：US12727304
申请日：2010-03-19
IPC分类号： H01L21/8249
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L27/0928 , H01L29/0821
摘要： A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed.
摘要翻译： 一种用于形成在半导体衬底上具有多个不同集电极掺杂密度的双极结型晶体管的工艺，以及包括具有多个不同集电极掺杂密度的双极结型晶体管的集成电路。 第一组晶体管在形成三阱期间形成，用于为也形成在半导体衬底上的互补金属氧化物半导体场效应晶体管提供三阱隔离。 在形成用于场效应晶体管的栅叠层之后的第二掺杂步骤期间，形成具有不同集电极掺杂密度的附加双极结型晶体管。 通过双极晶体管发射极窗口进行的种植体掺杂形成了与先前形成的双极晶体管不同的掺杂密度的双极晶体管。 根据本发明的一个实施例，形成具有六种不同集电极掺杂剂密度（并因此具有六种不同击穿特性）的双极结型晶体管。
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10.发明授权公开(公告)号：US07095094B2
公开(公告)日：2006-08-22
申请号：US10953894
申请日：2004-09-29
IPC分类号： H01L27/102
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L27/0928 , H01L29/0821
摘要： A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed.
摘要翻译： 一种用于形成在半导体衬底上具有多个不同集电极掺杂密度的双极结型晶体管的工艺，以及包括具有多个不同集电极掺杂密度的双极结型晶体管的集成电路。 第一组晶体管在形成三阱期间形成，用于为也形成在半导体衬底上的互补金属氧化物半导体场效应晶体管提供三阱隔离。 在形成用于场效应晶体管的栅叠层之后的第二掺杂步骤期间，形成具有不同集电极掺杂密度的附加双极结型晶体管。 通过双极晶体管发射极窗口进行的种植体掺杂形成了与先前形成的双极晶体管不同的掺杂密度的双极晶体管。 根据本发明的一个实施例，形成具有六种不同集电极掺杂剂密度（并因此具有六种不同击穿特性）的双极结型晶体管。
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