公开(公告)号：US20210036076A1

公开(公告)日：2021-02-04

申请号：US16895756

申请日：2020-06-08

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Seul Ki KIM ,  Seung Sok SON ,  Kap Soo YOON ,  Woo Geun LEE ,  Su Jung JUNG ,  Seung Ha CHOI

IPC: H01L27/32

Abstract: A display device includes a substrate having a display area and a pad area. A gate conductive layer disposed on the substrate includes a gate conductive metal layer and a gate capping layer. The gate conductive layer forms a gate electrode in the display area and a wire pad in the pad area that is exposed by a pad opening. An interlayer insulating film disposed on the gate conductive layer covers the gate electrode. A data conductive layer disposed on the interlayer insulating film in the display area includes source and drain electrodes. A passivation layer disposed on the data conductive layer covers the source and drain electrodes. A via layer is disposed on the passivation layer. A pixel electrode is disposed on the via layer. The pixel electrode is connected to the source electrode through a contact hole penetrating the via layer and the passivation layer.

公开(公告)号：US20240331608A1

公开(公告)日：2024-10-03

申请号：US18732585

申请日：2024-06-03

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam KIM ,  Sung Hoon LIM ,  Woo Geun LEE ,  Kyu Sik CHO ,  Jae Beom CHOI

IPC: G09G3/20 ,  G09G3/3233 ,  G09G3/3266

CPC classification number: G09G3/2092 ,  G09G3/3233 ,  G09G3/3266 ,  G09G2310/0202 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0286 ,  G09G2310/08

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US20240016011A1

公开(公告)日：2024-01-11

申请号：US18118746

申请日：2023-03-08

Applicant: Samsung Display Co., Ltd.

Inventor： Kwang Soo LEE ,  Sho Yeon KIM ,  Hyun KIM ,  Kap Soo YOON ,  Woo Geun LEE ,  Seung Ha CHOI

IPC: H10K59/131 ,  H10K59/12

CPC classification number: H10K59/131 ,  H10K59/1201

Abstract: A display device includes a first base portion, a first conductive layer comprising a lower light blocking layer on the first base portion, and a lower wiring spaced apart from the lower light blocking layer, a buffer layer disposed on the first conductive layer, a semiconductor layer disposed on the first buffer layer and comprising a first area, a second area on one side of the first area, and a third area on the other side of the first area, a gate insulating layer on the semiconductor layer, and a second conductive layer comprising a gate electrode overlapping the first area on the gate insulating layer, wherein conductivity of each of the first area and the second area is higher than conductivity of the first area, the third area is electrically connected to the lower wiring, and the second area is directly connected to the lower light blocking layer.

公开(公告)号：US20250024710A1

公开(公告)日：2025-01-16

申请号：US18616218

申请日：2024-03-26

Applicant: Samsung Display Co., Ltd.

Inventor： Dong Han KANG ,  Shin Hyuk YANG ,  Woo Geun LEE ,  Jee Hoon KIM ,  Sung Gwon MOON

IPC: H10K59/121 ,  H10K59/12 ,  H10K59/131 ,  H10K59/80 ,  H10K71/60

Abstract: A display device is disclosed that includes a substrate, a first metal layer disposed on the substrate, an active layer disposed on the first metal layer, a second metal layer disposed on the active layer, a third metal layer disposed on the second metal layer, a fourth metal layer disposed on the third metal layer, and a transistor and a capacitor disposed on the substrate. The transistor includes a gate electrode disposed in at least any one of the first metal layer and the second metal layer, and a drain electrode, a source electrode and an active region disposed in the active layer, The capacitor includes a first capacitor including a first electrode disposed in the first metal layer and a second electrode disposed in the second metal layer, a second capacitor including the second electrode and a third electrode disposed in the third metal layer, and a third capacitor including the third electrode and a fourth electrode disposed in the fourth metal layer.

公开(公告)号：US20240120342A1

公开(公告)日：2024-04-11

申请号：US18208263

申请日：2023-06-10

Applicant: Samsung Display Co., LTD.

Inventor： Sung Gwon MOON ,  Dong Han KANG ,  Jee Hoon KIM ,  Seung Sok SON ,  Shin Hyuk YANG ,  Woo Geun LEE

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/1244 ,  H01L27/1255 ,  H01L27/127

Abstract: A transistor array substrate includes a substrate, an active layer disposed on the substrate and including a channel region, a source region and a drain region, a gate insulating layer disposed on a part of the active layer, a gate electrode overlapping the channel region of the active layer and included in an electrode conductive layer which is disposed on the gate insulating layer, a source electrode included in the electrode conductive layer and in contact with a part of the source region of the active layer, and a drain electrode included in the electrode conductive layer and in contact with a part of the drain region of the active layer. The active layer includes an oxide semiconductor including crystals and is disposed as an island shape excluding a hole in a plan view.

公开(公告)号：US20220139965A1

公开(公告)日：2022-05-05

申请号：US17368200

申请日：2021-07-06

Applicant: Samsung Display Co., Ltd.

Inventor： Woo Bin LEE ,  Seok Hwan BANG ,  Seung Sok SON ,  Woo Geun LEE ,  Soo Jung CHAE

IPC: H01L27/12

Abstract: A display device includes a substrate and a transistor disposed on the substrate and including a semiconductor layer, wherein the semiconductor layer includes a mesh structure, and wherein a plurality of openings are formed in the semiconductor layer.

公开(公告)号：US20140332889A1

公开(公告)日：2014-11-13

申请号：US14012580

申请日：2013-08-28

Applicant: Samsung Display Co., Ltd.

Inventor： Seung-Ho JUNG ,  Young Joo CHOI ,  Joon Geol KIM ,  Kang Moon JO ,  Sho Yeon KIM ,  Byung Hwan CHU ,  Woo Geun LEE ,  Woo-Seok JEON

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1262 ,  H01L27/1288

Abstract: A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.

Abstract translation: 公开了薄膜晶体管阵列面板。 薄膜晶体管阵列面板可以包括设置在基板上并包括栅电极的栅极线，包括设置在基板上的氧化物半导体的半导体层，设置在基板上的数据布线层，并且包括与栅极线交叉的数据线 连接到数据线的源电极和面对源电极的漏电极，覆盖源电极和漏电极的聚合物层和设置在聚合物层上的钝化层。 数据布线层可以包括铜或铜合金，并且聚合物层可以包括碳氟化合物。

公开(公告)号：US20230245612A1

公开(公告)日：2023-08-03

申请号：US18132704

申请日：2023-04-10

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam KIM ,  Sung Hoon LIM ,  Woo Geun LEE ,  Kyu Sik CHO ,  Jae Beom CHOI

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G3/3266 ,  G09G2310/08 ,  G09G2310/0267 ,  G09G2310/0275

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US20220199742A1

公开(公告)日：2022-06-23

申请号：US17407407

申请日：2021-08-20

Applicant: Samsung Display Co., LTD.

Inventor： Young Jae JEON ,  Woo Geun LEE ,  Jae Beom CHOI ,  Jong-In KIM ,  Jin-Won LEE

IPC: H01L27/32 ,  H01L51/52

Abstract: A display device includes a semiconductor layer of a driving transistor; a semiconductor layer of a switching transistor; a semiconductor layer of an initialization transistor; a gate electrode of the driving transistor overlapping a semiconductor layer of the driving transistor; a lower storage electrode connected to the semiconductor layer of the switching transistor; an upper storage electrode connected to the semiconductor layer of the driving transistor, a light blocking pattern, and the semiconductor layer of the initialization transistor, and overlapping the lower storage electrode; a semiconductor layer of a first auxiliary transistor adjacent the semiconductor layer of the switching transistor and/or the semiconductor layer of the initialization transistor; a first electrode of the first auxiliary transistor connected to the semiconductor layer of the first auxiliary transistor; and a second electrode of the first auxiliary transistor connected to the semiconductor layer of the first auxiliary transistor.

公开(公告)号：US20220140059A1

公开(公告)日：2022-05-05

申请号：US17475950

申请日：2021-09-15

Applicant: Samsung Display Co., LTD.

Inventor： Jong In KIM ,  Hyun Seong KANG ,  Joon Geol KIM ,  Seung Sok SON ,  Woo Geun LEE ,  Young Jae JEON ,  Soo Jung CHAE ,  Ji Yun HONG

IPC: H01L27/32 ,  H01L51/00

Abstract: A display device includes a pixel electrode disposed on a first surface of a substrate, a light emitting layer disposed on the pixel electrode, a common electrode disposed on the light emitting layer, a supply voltage line disposed on the first surface of the substrate and applying a voltage to the common electrode, a first auxiliary conductive layer disposed on a second surface of the substrate, and a first connection conductive layer at least partially disposed on a side surface of the substrate and electrically connecting the first auxiliary conductive layer to the supply voltage line.