公开(公告)号：US20140328023A1

公开(公告)日：2014-11-06

申请号：US14153327

申请日：2014-01-13

Applicant: Samsung Electronics Co., Ltd

Inventor： IN-HO CHOI ,  YONG-HOON KIM ,  SEONG-HO SHIN

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29387 ,  H01L2224/29388 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1615 ,  H01L2924/16251 ,  H01L2924/16724 ,  H01L2924/16747 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor package includes a substrate, a semiconductor chip located on a top surface of the substrate, signal lines formed on the top surface of the substrate and configured to allow different types of signals to input/output thereto/therefrom, a ground line unit formed on the top surface of the substrate and configured to divide the signal lines into signal lines to/from which the same types of signals are input/output to be isolated from one another, barrier walls configured to contact the ground line unit, and a heat dissipation unit disposed on the semiconductor chip, wherein the ground line unit includes diagonal ground lines located in diagonal directions of the substrate about the semiconductor chip, and the heat dissipation unit includes a thermal interface material (TIM) located on a top surface of the semiconductor chip, and a heat dissipation plate configured to cover the TIM and the substrate.

Abstract translation: 半导体封装包括衬底，位于衬底的顶表面上的半导体芯片，形成在衬底的顶表面上并被配置为允许不同类型的信号从其输入/输出的信号线，形成的接地线单元 在基板的顶表面上，并且将信号线分成信号线，以使相同类型的信号被输入/输出为彼此隔离的信号线，被配置为接触地线单元的阻挡壁和热量 设置在半导体芯片上的散热单元，其中接地线单元包括位于半导体芯片周围的基板的对角线方向的对角线，而散热单元包括位于半导体芯片顶表面上的热界面材料（TIM） 芯片，以及配置成覆盖TIM和基板的散热板。

公开(公告)号：US20140175679A1

公开(公告)日：2014-06-26

申请号：US14190079

申请日：2014-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： HEUNG-KYU KWON ,  SEONG-HO SHIN ,  YUN-SEOK CHOI ,  YONG-HOON KIM

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit.

Abstract translation: 封装堆叠结构可以是上封装包括具有第一边缘和与第一边缘相对的第二边缘的上封装基板。 上封装衬底具有布置在第一边缘附近的第一区域和布置在第二边缘附近的第二区域。 第一上半导体器件安装在上封装衬底上。 封装堆叠结构还可以包括具有下封装衬底和下半导体器件的下封装。 下封装通过多个封装间连接器连接到上封装。 多个包装间连接器可以包括被配置为传送数据信号的第一包装间连接器; 配置成发送地址/控制信号的第二串联连接器连接器; 第三组件间连接器，被配置为提供地址/控制电路的电源电压; 以及被配置为提供数据电路的电源电压的第四组件间连接器。