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    INTEGRATED CIRCUITS INCLUDING MULTI-LAYER CONDUCTING LINES
    2.
    发明申请
    INTEGRATED CIRCUITS INCLUDING MULTI-LAYER CONDUCTING LINES 审中-公开

    公开(公告)号：US20200075478A1

    公开(公告)日：2020-03-05

    申请号：US16519725

    申请日：2019-07-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tae-hyung Kim ,  Chan-Ho Lee

    IPC: H01L23/522 ,  G11C5/06 ,  G11C5/02 ,  H01L25/065

    Abstract: An integrated circuit includes a plurality of layers stacked in a first direction, a plurality of unit circuits at least partially overlapping each other in a second direction that is perpendicular to the first direction and configured to operate in parallel with one another, control circuitry configured to generate a control signal to control the plurality of unit circuits, and a multi-layer conducting line configured to transfer the control signal from the control circuitry to the plurality of unit circuits. The multi-layer conducting line may be integrally formed in a wiring layer and a via layer and extends in the second direction. The wiring layer and the via layer may be adjacent to each other.

    Integrated circuits including multi-layer conducting lines
    3.
    发明授权
    Integrated circuits including multi-layer conducting lines 有权

    公开(公告)号：US10978384B2

    公开(公告)日：2021-04-13

    申请号：US16519725

    申请日：2019-07-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tae-hyung Kim ,  Chan-Ho Lee

    IPC: H01L23/522 ,  G11C5/06 ,  H01L25/065 ,  G11C5/02 ,  G02B6/43

    Abstract: An integrated circuit includes a plurality of layers stacked in a first direction, a plurality of unit circuits at least partially overlapping each other in a second direction that is perpendicular to the first direction and configured to operate in parallel with one another, control circuitry configured to generate a control signal to control the plurality of unit circuits, and a multi-layer conducting line configured to transfer the control signal from the control circuitry to the plurality of unit circuits. The multi-layer conducting line may be integrally formed in a wiring layer and a via layer and extends in the second direction. The wiring layer and the via layer may be adjacent to each other.

    Semiconductor chip including a bump structure and semiconductor package including the same
    6.
    发明授权
    Semiconductor chip including a bump structure and semiconductor package including the same 有权

    公开(公告)号：US10930610B2

    公开(公告)日：2021-02-23

    申请号：US16283906

    申请日：2019-02-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jin-Kuk Bae ,  Hyun-Soo Chung ,  Han-Sung Ryu ,  In-Young Lee ,  Chan-Ho Lee

    IPC: H01L23/00 ,  H01L23/48

    Abstract: A semiconductor chip includes a substrate having a low-k material layer. An electrode pad is disposed the substrate. A first protection layer at least partially surrounds the electrode pad. The first protection layer includes a first opening at an upper portion thereof. A buffer pad is electrically connected to the electrode pad. A second protection layer at least partially surrounds the buffer pad. The second protection layer includes a second opening at an upper portion thereof. A pillar layer and a solder layer are sequentially stacked on the buffer pad. A thickness of the buffer pad is greater than a thickness of the electrode pad. A width of the first opening in a first direction parallel to an upper surface of the semiconductor substrate is equal to or greater than a width of the second opening in the first direction.

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